SURF  1.0
Generics | Ports | Libraries | Use Clauses
Gth7Core Entity Reference
xilinx » 7Series » gth7
+ Inheritance diagram for Gth7Core:
+ Collaboration diagram for Gth7Core:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
SIM_GTRESET_SPEEDUP_G  string := " FALSE "
SIM_VERSION_G  string := " 2.0 "
SIMULATION_G  boolean := false
STABLE_CLOCK_PERIOD_G  real := 4 . 0E - 9
CPLL_REFCLK_SEL_G  bit_vector := " 001 "
CPLL_FBDIV_G  integer := 4
CPLL_FBDIV_45_G  integer := 5
CPLL_REFCLK_DIV_G  integer := 1
RXOUT_DIV_G  integer := 2
TXOUT_DIV_G  integer := 2
RX_CLK25_DIV_G  integer := 5
TX_CLK25_DIV_G  integer := 5
PMA_RSV_G  bit_vector := X " 00000080 "
RX_OS_CFG_G  bit_vector := " 0000010000000 "
RXCDR_CFG_G  bit_vector := x " 0002007FE1000C2200018 "
TX_PLL_G  string := " CPLL "
RX_PLL_G  string := " CPLL "
TX_EXT_DATA_WIDTH_G  integer := 16
TX_INT_DATA_WIDTH_G  integer := 20
TX_8B10B_EN_G  boolean := true
RX_EXT_DATA_WIDTH_G  integer := 16
RX_INT_DATA_WIDTH_G  integer := 20
RX_8B10B_EN_G  boolean := true
TX_BUF_EN_G  boolean := true
TX_OUTCLK_SRC_G  string := " PLLREFCLK "
TX_DLY_BYPASS_G  sl := ' 1 '
TX_PHASE_ALIGN_G  string := " AUTO "
TX_BUF_ADDR_MODE_G  string := " FAST "
RX_BUF_EN_G  boolean := true
RX_OUTCLK_SRC_G  string := " PLLREFCLK "
RX_USRCLK_SRC_G  string := " RXOUTCLK "
RX_DLY_BYPASS_G  sl := ' 1 '
RX_DDIEN_G  sl := ' 0 '
RX_BUF_ADDR_MODE_G  string := " FAST "
RX_ALIGN_MODE_G  string := " GT "
ALIGN_COMMA_DOUBLE_G  string := " FALSE "
ALIGN_COMMA_ENABLE_G  bit_vector := " 1111111111 "
ALIGN_COMMA_WORD_G  integer := 2
ALIGN_MCOMMA_DET_G  string := " FALSE "
ALIGN_MCOMMA_VALUE_G  bit_vector := " 1010000011 "
ALIGN_MCOMMA_EN_G  sl := ' 0 '
ALIGN_PCOMMA_DET_G  string := " FALSE "
ALIGN_PCOMMA_VALUE_G  bit_vector := " 0101111100 "
ALIGN_PCOMMA_EN_G  sl := ' 0 '
SHOW_REALIGN_COMMA_G  string := " FALSE "
RXSLIDE_MODE_G  string := " PCS "
FIXED_COMMA_EN_G  slv ( 3 downto 0 ) := " 0011 "
FIXED_ALIGN_COMMA_0_G  slv := " ----------0101111100 "
FIXED_ALIGN_COMMA_1_G  slv := " ----------1010000011 "
FIXED_ALIGN_COMMA_2_G  slv := " XXXXXXXXXXXXXXXXXXXX "
FIXED_ALIGN_COMMA_3_G  slv := " XXXXXXXXXXXXXXXXXXXX "
RX_DISPERR_SEQ_MATCH_G  string := " TRUE "
DEC_MCOMMA_DETECT_G  string := " TRUE "
DEC_PCOMMA_DETECT_G  string := " TRUE "
DEC_VALID_COMMA_ONLY_G  string := " FALSE "
CBCC_DATA_SOURCE_SEL_G  string := " DECODED "
CLK_COR_SEQ_2_USE_G  string := " FALSE "
CLK_COR_KEEP_IDLE_G  string := " FALSE "
CLK_COR_MAX_LAT_G  integer := 9
CLK_COR_MIN_LAT_G  integer := 7
CLK_COR_PRECEDENCE_G  string := " TRUE "
CLK_COR_REPEAT_WAIT_G  integer := 0
CLK_COR_SEQ_LEN_G  integer := 1
CLK_COR_SEQ_1_ENABLE_G  bit_vector := " 1111 "
CLK_COR_SEQ_1_1_G  bit_vector := " 0100000000 "
CLK_COR_SEQ_1_2_G  bit_vector := " 0000000000 "
CLK_COR_SEQ_1_3_G  bit_vector := " 0000000000 "
CLK_COR_SEQ_1_4_G  bit_vector := " 0000000000 "
CLK_CORRECT_USE_G  string := " FALSE "
CLK_COR_SEQ_2_ENABLE_G  bit_vector := " 0000 "
CLK_COR_SEQ_2_1_G  bit_vector := " 0100000000 "
CLK_COR_SEQ_2_2_G  bit_vector := " 0000000000 "
CLK_COR_SEQ_2_3_G  bit_vector := " 0000000000 "
CLK_COR_SEQ_2_4_G  bit_vector := " 0000000000 "
RX_CHAN_BOND_EN_G  boolean := false
RX_CHAN_BOND_MASTER_G  boolean := false
CHAN_BOND_KEEP_ALIGN_G  string := " FALSE "
CHAN_BOND_MAX_SKEW_G  integer := 1
CHAN_BOND_SEQ_LEN_G  integer := 1
CHAN_BOND_SEQ_1_1_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_2_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_3_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_4_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_1_ENABLE_G  bit_vector := " 1111 "
CHAN_BOND_SEQ_2_1_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_2_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_3_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_4_G  bit_vector := " 0000000000 "
CHAN_BOND_SEQ_2_ENABLE_G  bit_vector := " 0000 "
CHAN_BOND_SEQ_2_USE_G  string := " FALSE "
FTS_DESKEW_SEQ_ENABLE_G  bit_vector := " 1111 "
FTS_LANE_DESKEW_CFG_G  bit_vector := " 1111 "
FTS_LANE_DESKEW_EN_G  string := " FALSE "
RX_EQUALIZER_G  string := " LPM "
RX_CM_TRIM_G  bit_vector := " 1000 "
RX_DFE_LPM_CFG_G  bit_vector := x " 0080 "
RXDFELFOVRDEN_G  sl := ' 0 '
RXDFEXYDEN_G  sl := ' 1 '

Ports

stableClkIn   in sl
cPllRefClkIn   in sl := ' 0 '
cPllLockOut   out sl
qPllRefClkIn   in sl := ' 0 '
qPllClkIn   in sl := ' 0 '
qPllLockIn   in sl := ' 0 '
qPllRefClkLostIn   in sl := ' 0 '
qPllResetOut   out sl
gtRxRefClkBufg   in sl := ' 0 '
gtTxP   out sl
gtTxN   out sl
gtRxP   in sl
gtRxN   in sl
rxOutClkOut   out sl
rxUsrClkIn   in sl
rxUsrClk2In   in sl
rxUserRdyOut   out sl
rxMmcmResetOut   out sl
rxMmcmLockedIn   in sl := ' 1 '
rxUserResetIn   in sl
rxResetDoneOut   out sl
rxDataValidIn   in sl := ' 1 '
rxSlideIn   in sl := ' 0 '
rxDataOut   out slv ( RX_EXT_DATA_WIDTH_G - 1 downto 0 )
rxCharIsKOut   out slv ( ( RX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
rxDecErrOut   out slv ( ( RX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
rxDispErrOut   out slv ( ( RX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
rxPolarityIn   in sl := ' 0 '
rxBufStatusOut   out slv ( 2 downto 0 )
rxChBondLevelIn   in slv ( 2 downto 0 ) := " 000 "
rxChBondIn   in slv ( 4 downto 0 ) := " 00000 "
rxChBondOut   out slv ( 4 downto 0 )
txOutClkOut   out sl
txUsrClkIn   in sl
txUsrClk2In   in sl
txUserRdyOut   out sl
txMmcmResetOut   out sl
txMmcmLockedIn   in sl := ' 1 '
txUserResetIn   in sl
txResetDoneOut   out sl
txDataIn   in slv ( TX_EXT_DATA_WIDTH_G - 1 downto 0 )
txCharIsKIn   in slv ( ( TX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
txBufStatusOut   out slv ( 1 downto 0 )
txPolarityIn   in sl := ' 0 '
txPowerDown   in slv ( 1 downto 0 ) := " 00 "
rxPowerDown   in slv ( 1 downto 0 ) := " 00 "
loopbackIn   in slv ( 2 downto 0 ) := " 000 "
txPreCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl   in slv ( 3 downto 0 ) := " 1000 "
drpGnt   out sl
drpRdy   out sl
drpEn   in sl := ' 0 '
drpWe   in sl := ' 0 '
drpAddr   in slv ( 8 downto 0 ) := " 000000000 "
drpDi   in slv ( 15 downto 0 ) := X " 0000 "
drpDo   out slv ( 15 downto 0 )

Detailed Description

See also
entity

Definition at line 28 of file Gth7Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file Gth7Core.vhd.

◆ SIM_GTRESET_SPEEDUP_G

SIM_GTRESET_SPEEDUP_G string := " FALSE "
Generic

Definition at line 32 of file Gth7Core.vhd.

◆ SIM_VERSION_G

SIM_VERSION_G string := " 2.0 "
Generic

Definition at line 33 of file Gth7Core.vhd.

◆ SIMULATION_G

SIMULATION_G boolean := false
Generic

Definition at line 34 of file Gth7Core.vhd.

◆ STABLE_CLOCK_PERIOD_G

STABLE_CLOCK_PERIOD_G real := 4 . 0E - 9
Generic

Definition at line 35 of file Gth7Core.vhd.

◆ CPLL_REFCLK_SEL_G

CPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 37 of file Gth7Core.vhd.

◆ CPLL_FBDIV_G

CPLL_FBDIV_G integer := 4
Generic

Definition at line 38 of file Gth7Core.vhd.

◆ CPLL_FBDIV_45_G

CPLL_FBDIV_45_G integer := 5
Generic

Definition at line 39 of file Gth7Core.vhd.

◆ CPLL_REFCLK_DIV_G

CPLL_REFCLK_DIV_G integer := 1
Generic

Definition at line 40 of file Gth7Core.vhd.

◆ RXOUT_DIV_G

RXOUT_DIV_G integer := 2
Generic

Definition at line 41 of file Gth7Core.vhd.

◆ TXOUT_DIV_G

TXOUT_DIV_G integer := 2
Generic

Definition at line 42 of file Gth7Core.vhd.

◆ RX_CLK25_DIV_G

RX_CLK25_DIV_G integer := 5
Generic

Definition at line 43 of file Gth7Core.vhd.

◆ TX_CLK25_DIV_G

TX_CLK25_DIV_G integer := 5
Generic

Definition at line 44 of file Gth7Core.vhd.

◆ PMA_RSV_G

PMA_RSV_G bit_vector := X " 00000080 "
Generic

Definition at line 45 of file Gth7Core.vhd.

◆ RX_OS_CFG_G

RX_OS_CFG_G bit_vector := " 0000010000000 "
Generic

Definition at line 46 of file Gth7Core.vhd.

◆ RXCDR_CFG_G

RXCDR_CFG_G bit_vector := x " 0002007FE1000C2200018 "
Generic

Definition at line 47 of file Gth7Core.vhd.

◆ TX_PLL_G

TX_PLL_G string := " CPLL "
Generic

Definition at line 49 of file Gth7Core.vhd.

◆ RX_PLL_G

RX_PLL_G string := " CPLL "
Generic

Definition at line 50 of file Gth7Core.vhd.

◆ TX_EXT_DATA_WIDTH_G

TX_EXT_DATA_WIDTH_G integer := 16
Generic

Definition at line 52 of file Gth7Core.vhd.

◆ TX_INT_DATA_WIDTH_G

TX_INT_DATA_WIDTH_G integer := 20
Generic

Definition at line 53 of file Gth7Core.vhd.

◆ TX_8B10B_EN_G

TX_8B10B_EN_G boolean := true
Generic

Definition at line 54 of file Gth7Core.vhd.

◆ RX_EXT_DATA_WIDTH_G

RX_EXT_DATA_WIDTH_G integer := 16
Generic

Definition at line 55 of file Gth7Core.vhd.

◆ RX_INT_DATA_WIDTH_G

RX_INT_DATA_WIDTH_G integer := 20
Generic

Definition at line 56 of file Gth7Core.vhd.

◆ RX_8B10B_EN_G

RX_8B10B_EN_G boolean := true
Generic

Definition at line 57 of file Gth7Core.vhd.

◆ TX_BUF_EN_G

TX_BUF_EN_G boolean := true
Generic

Definition at line 59 of file Gth7Core.vhd.

◆ TX_OUTCLK_SRC_G

TX_OUTCLK_SRC_G string := " PLLREFCLK "
Generic

Definition at line 60 of file Gth7Core.vhd.

◆ TX_DLY_BYPASS_G

TX_DLY_BYPASS_G sl := ' 1 '
Generic

Definition at line 61 of file Gth7Core.vhd.

◆ TX_PHASE_ALIGN_G

TX_PHASE_ALIGN_G string := " AUTO "
Generic

Definition at line 62 of file Gth7Core.vhd.

◆ TX_BUF_ADDR_MODE_G

TX_BUF_ADDR_MODE_G string := " FAST "
Generic

Definition at line 63 of file Gth7Core.vhd.

◆ RX_BUF_EN_G

RX_BUF_EN_G boolean := true
Generic

Definition at line 64 of file Gth7Core.vhd.

◆ RX_OUTCLK_SRC_G

RX_OUTCLK_SRC_G string := " PLLREFCLK "
Generic

Definition at line 65 of file Gth7Core.vhd.

◆ RX_USRCLK_SRC_G

RX_USRCLK_SRC_G string := " RXOUTCLK "
Generic

Definition at line 66 of file Gth7Core.vhd.

◆ RX_DLY_BYPASS_G

RX_DLY_BYPASS_G sl := ' 1 '
Generic

Definition at line 67 of file Gth7Core.vhd.

◆ RX_DDIEN_G

RX_DDIEN_G sl := ' 0 '
Generic

Definition at line 68 of file Gth7Core.vhd.

◆ RX_BUF_ADDR_MODE_G

RX_BUF_ADDR_MODE_G string := " FAST "
Generic

Definition at line 69 of file Gth7Core.vhd.

◆ RX_ALIGN_MODE_G

RX_ALIGN_MODE_G string := " GT "
Generic

Definition at line 71 of file Gth7Core.vhd.

◆ ALIGN_COMMA_DOUBLE_G

ALIGN_COMMA_DOUBLE_G string := " FALSE "
Generic

Definition at line 72 of file Gth7Core.vhd.

◆ ALIGN_COMMA_ENABLE_G

ALIGN_COMMA_ENABLE_G bit_vector := " 1111111111 "
Generic

Definition at line 73 of file Gth7Core.vhd.

◆ ALIGN_COMMA_WORD_G

ALIGN_COMMA_WORD_G integer := 2
Generic

Definition at line 74 of file Gth7Core.vhd.

◆ ALIGN_MCOMMA_DET_G

ALIGN_MCOMMA_DET_G string := " FALSE "
Generic

Definition at line 75 of file Gth7Core.vhd.

◆ ALIGN_MCOMMA_VALUE_G

ALIGN_MCOMMA_VALUE_G bit_vector := " 1010000011 "
Generic

Definition at line 76 of file Gth7Core.vhd.

◆ ALIGN_MCOMMA_EN_G

ALIGN_MCOMMA_EN_G sl := ' 0 '
Generic

Definition at line 77 of file Gth7Core.vhd.

◆ ALIGN_PCOMMA_DET_G

ALIGN_PCOMMA_DET_G string := " FALSE "
Generic

Definition at line 78 of file Gth7Core.vhd.

◆ ALIGN_PCOMMA_VALUE_G

ALIGN_PCOMMA_VALUE_G bit_vector := " 0101111100 "
Generic

Definition at line 79 of file Gth7Core.vhd.

◆ ALIGN_PCOMMA_EN_G

ALIGN_PCOMMA_EN_G sl := ' 0 '
Generic

Definition at line 80 of file Gth7Core.vhd.

◆ SHOW_REALIGN_COMMA_G

SHOW_REALIGN_COMMA_G string := " FALSE "
Generic

Definition at line 81 of file Gth7Core.vhd.

◆ RXSLIDE_MODE_G

RXSLIDE_MODE_G string := " PCS "
Generic

Definition at line 82 of file Gth7Core.vhd.

◆ FIXED_COMMA_EN_G

FIXED_COMMA_EN_G slv ( 3 downto 0 ) := " 0011 "
Generic

Definition at line 84 of file Gth7Core.vhd.

◆ FIXED_ALIGN_COMMA_0_G

FIXED_ALIGN_COMMA_0_G slv := " ----------0101111100 "
Generic

Definition at line 85 of file Gth7Core.vhd.

◆ FIXED_ALIGN_COMMA_1_G

FIXED_ALIGN_COMMA_1_G slv := " ----------1010000011 "
Generic

Definition at line 86 of file Gth7Core.vhd.

◆ FIXED_ALIGN_COMMA_2_G

FIXED_ALIGN_COMMA_2_G slv := " XXXXXXXXXXXXXXXXXXXX "
Generic

Definition at line 87 of file Gth7Core.vhd.

◆ FIXED_ALIGN_COMMA_3_G

FIXED_ALIGN_COMMA_3_G slv := " XXXXXXXXXXXXXXXXXXXX "
Generic

Definition at line 88 of file Gth7Core.vhd.

◆ RX_DISPERR_SEQ_MATCH_G

RX_DISPERR_SEQ_MATCH_G string := " TRUE "
Generic

Definition at line 90 of file Gth7Core.vhd.

◆ DEC_MCOMMA_DETECT_G

DEC_MCOMMA_DETECT_G string := " TRUE "
Generic

Definition at line 91 of file Gth7Core.vhd.

◆ DEC_PCOMMA_DETECT_G

DEC_PCOMMA_DETECT_G string := " TRUE "
Generic

Definition at line 92 of file Gth7Core.vhd.

◆ DEC_VALID_COMMA_ONLY_G

DEC_VALID_COMMA_ONLY_G string := " FALSE "
Generic

Definition at line 93 of file Gth7Core.vhd.

◆ CBCC_DATA_SOURCE_SEL_G

CBCC_DATA_SOURCE_SEL_G string := " DECODED "
Generic

Definition at line 95 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_2_USE_G

CLK_COR_SEQ_2_USE_G string := " FALSE "
Generic

Definition at line 96 of file Gth7Core.vhd.

◆ CLK_COR_KEEP_IDLE_G

CLK_COR_KEEP_IDLE_G string := " FALSE "
Generic

Definition at line 97 of file Gth7Core.vhd.

◆ CLK_COR_MAX_LAT_G

CLK_COR_MAX_LAT_G integer := 9
Generic

Definition at line 98 of file Gth7Core.vhd.

◆ CLK_COR_MIN_LAT_G

CLK_COR_MIN_LAT_G integer := 7
Generic

Definition at line 99 of file Gth7Core.vhd.

◆ CLK_COR_PRECEDENCE_G

CLK_COR_PRECEDENCE_G string := " TRUE "
Generic

Definition at line 100 of file Gth7Core.vhd.

◆ CLK_COR_REPEAT_WAIT_G

CLK_COR_REPEAT_WAIT_G integer := 0
Generic

Definition at line 101 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_LEN_G

CLK_COR_SEQ_LEN_G integer := 1
Generic

Definition at line 102 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_1_ENABLE_G

CLK_COR_SEQ_1_ENABLE_G bit_vector := " 1111 "
Generic

Definition at line 103 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_1_1_G

CLK_COR_SEQ_1_1_G bit_vector := " 0100000000 "
Generic

Definition at line 104 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_1_2_G

CLK_COR_SEQ_1_2_G bit_vector := " 0000000000 "
Generic

Definition at line 105 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_1_3_G

CLK_COR_SEQ_1_3_G bit_vector := " 0000000000 "
Generic

Definition at line 106 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_1_4_G

CLK_COR_SEQ_1_4_G bit_vector := " 0000000000 "
Generic

Definition at line 107 of file Gth7Core.vhd.

◆ CLK_CORRECT_USE_G

CLK_CORRECT_USE_G string := " FALSE "
Generic

Definition at line 108 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_2_ENABLE_G

CLK_COR_SEQ_2_ENABLE_G bit_vector := " 0000 "
Generic

Definition at line 109 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_2_1_G

CLK_COR_SEQ_2_1_G bit_vector := " 0100000000 "
Generic

Definition at line 110 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_2_2_G

CLK_COR_SEQ_2_2_G bit_vector := " 0000000000 "
Generic

Definition at line 111 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_2_3_G

CLK_COR_SEQ_2_3_G bit_vector := " 0000000000 "
Generic

Definition at line 112 of file Gth7Core.vhd.

◆ CLK_COR_SEQ_2_4_G

CLK_COR_SEQ_2_4_G bit_vector := " 0000000000 "
Generic

Definition at line 113 of file Gth7Core.vhd.

◆ RX_CHAN_BOND_EN_G

RX_CHAN_BOND_EN_G boolean := false
Generic

Definition at line 115 of file Gth7Core.vhd.

◆ RX_CHAN_BOND_MASTER_G

RX_CHAN_BOND_MASTER_G boolean := false
Generic

Definition at line 116 of file Gth7Core.vhd.

◆ CHAN_BOND_KEEP_ALIGN_G

CHAN_BOND_KEEP_ALIGN_G string := " FALSE "
Generic

Definition at line 117 of file Gth7Core.vhd.

◆ CHAN_BOND_MAX_SKEW_G

CHAN_BOND_MAX_SKEW_G integer := 1
Generic

Definition at line 118 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_LEN_G

CHAN_BOND_SEQ_LEN_G integer := 1
Generic

Definition at line 119 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_1_1_G

CHAN_BOND_SEQ_1_1_G bit_vector := " 0000000000 "
Generic

Definition at line 120 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_1_2_G

CHAN_BOND_SEQ_1_2_G bit_vector := " 0000000000 "
Generic

Definition at line 121 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_1_3_G

CHAN_BOND_SEQ_1_3_G bit_vector := " 0000000000 "
Generic

Definition at line 122 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_1_4_G

CHAN_BOND_SEQ_1_4_G bit_vector := " 0000000000 "
Generic

Definition at line 123 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_1_ENABLE_G

CHAN_BOND_SEQ_1_ENABLE_G bit_vector := " 1111 "
Generic

Definition at line 124 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_2_1_G

CHAN_BOND_SEQ_2_1_G bit_vector := " 0000000000 "
Generic

Definition at line 125 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_2_2_G

CHAN_BOND_SEQ_2_2_G bit_vector := " 0000000000 "
Generic

Definition at line 126 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_2_3_G

CHAN_BOND_SEQ_2_3_G bit_vector := " 0000000000 "
Generic

Definition at line 127 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_2_4_G

CHAN_BOND_SEQ_2_4_G bit_vector := " 0000000000 "
Generic

Definition at line 128 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_2_ENABLE_G

CHAN_BOND_SEQ_2_ENABLE_G bit_vector := " 0000 "
Generic

Definition at line 129 of file Gth7Core.vhd.

◆ CHAN_BOND_SEQ_2_USE_G

CHAN_BOND_SEQ_2_USE_G string := " FALSE "
Generic

Definition at line 130 of file Gth7Core.vhd.

◆ FTS_DESKEW_SEQ_ENABLE_G

FTS_DESKEW_SEQ_ENABLE_G bit_vector := " 1111 "
Generic

Definition at line 131 of file Gth7Core.vhd.

◆ FTS_LANE_DESKEW_CFG_G

FTS_LANE_DESKEW_CFG_G bit_vector := " 1111 "
Generic

Definition at line 132 of file Gth7Core.vhd.

◆ FTS_LANE_DESKEW_EN_G

FTS_LANE_DESKEW_EN_G string := " FALSE "
Generic

Definition at line 133 of file Gth7Core.vhd.

◆ RX_EQUALIZER_G

RX_EQUALIZER_G string := " LPM "
Generic

Definition at line 135 of file Gth7Core.vhd.

◆ RX_CM_TRIM_G

RX_CM_TRIM_G bit_vector := " 1000 "
Generic

Definition at line 136 of file Gth7Core.vhd.

◆ RX_DFE_LPM_CFG_G

RX_DFE_LPM_CFG_G bit_vector := x " 0080 "
Generic

Definition at line 137 of file Gth7Core.vhd.

◆ RXDFELFOVRDEN_G

RXDFELFOVRDEN_G sl := ' 0 '
Generic

Definition at line 138 of file Gth7Core.vhd.

◆ RXDFEXYDEN_G

RXDFEXYDEN_G sl := ' 1 '
Generic

Definition at line 139 of file Gth7Core.vhd.

◆ stableClkIn

stableClkIn in sl
Port

Definition at line 141 of file Gth7Core.vhd.

◆ cPllRefClkIn

cPllRefClkIn in sl := ' 0 '
Port

Definition at line 142 of file Gth7Core.vhd.

◆ cPllLockOut

cPllLockOut out sl
Port

Definition at line 143 of file Gth7Core.vhd.

◆ qPllRefClkIn

qPllRefClkIn in sl := ' 0 '
Port

Definition at line 144 of file Gth7Core.vhd.

◆ qPllClkIn

qPllClkIn in sl := ' 0 '
Port

Definition at line 145 of file Gth7Core.vhd.

◆ qPllLockIn

qPllLockIn in sl := ' 0 '
Port

Definition at line 146 of file Gth7Core.vhd.

◆ qPllRefClkLostIn

qPllRefClkLostIn in sl := ' 0 '
Port

Definition at line 147 of file Gth7Core.vhd.

◆ qPllResetOut

qPllResetOut out sl
Port

Definition at line 148 of file Gth7Core.vhd.

◆ gtRxRefClkBufg

gtRxRefClkBufg in sl := ' 0 '
Port

Definition at line 149 of file Gth7Core.vhd.

◆ gtTxP

gtTxP out sl
Port

Definition at line 151 of file Gth7Core.vhd.

◆ gtTxN

gtTxN out sl
Port

Definition at line 152 of file Gth7Core.vhd.

◆ gtRxP

gtRxP in sl
Port

Definition at line 153 of file Gth7Core.vhd.

◆ gtRxN

gtRxN in sl
Port

Definition at line 154 of file Gth7Core.vhd.

◆ rxOutClkOut

rxOutClkOut out sl
Port

Definition at line 156 of file Gth7Core.vhd.

◆ rxUsrClkIn

rxUsrClkIn in sl
Port

Definition at line 157 of file Gth7Core.vhd.

◆ rxUsrClk2In

rxUsrClk2In in sl
Port

Definition at line 158 of file Gth7Core.vhd.

◆ rxUserRdyOut

rxUserRdyOut out sl
Port

Definition at line 159 of file Gth7Core.vhd.

◆ rxMmcmResetOut

rxMmcmResetOut out sl
Port

Definition at line 160 of file Gth7Core.vhd.

◆ rxMmcmLockedIn

rxMmcmLockedIn in sl := ' 1 '
Port

Definition at line 161 of file Gth7Core.vhd.

◆ rxUserResetIn

rxUserResetIn in sl
Port

Definition at line 163 of file Gth7Core.vhd.

◆ rxResetDoneOut

rxResetDoneOut out sl
Port

Definition at line 164 of file Gth7Core.vhd.

◆ rxDataValidIn

rxDataValidIn in sl := ' 1 '
Port

Definition at line 166 of file Gth7Core.vhd.

◆ rxSlideIn

rxSlideIn in sl := ' 0 '
Port

Definition at line 167 of file Gth7Core.vhd.

◆ rxDataOut

rxDataOut out slv ( RX_EXT_DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 169 of file Gth7Core.vhd.

◆ rxCharIsKOut

rxCharIsKOut out slv ( ( RX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
Port

Definition at line 170 of file Gth7Core.vhd.

◆ rxDecErrOut

rxDecErrOut out slv ( ( RX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
Port

Definition at line 171 of file Gth7Core.vhd.

◆ rxDispErrOut

rxDispErrOut out slv ( ( RX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
Port

Definition at line 172 of file Gth7Core.vhd.

◆ rxPolarityIn

rxPolarityIn in sl := ' 0 '
Port

Definition at line 173 of file Gth7Core.vhd.

◆ rxBufStatusOut

rxBufStatusOut out slv ( 2 downto 0 )
Port

Definition at line 174 of file Gth7Core.vhd.

◆ rxChBondLevelIn

rxChBondLevelIn in slv ( 2 downto 0 ) := " 000 "
Port

Definition at line 176 of file Gth7Core.vhd.

◆ rxChBondIn

rxChBondIn in slv ( 4 downto 0 ) := " 00000 "
Port

Definition at line 177 of file Gth7Core.vhd.

◆ rxChBondOut

rxChBondOut out slv ( 4 downto 0 )
Port

Definition at line 178 of file Gth7Core.vhd.

◆ txOutClkOut

txOutClkOut out sl
Port

Definition at line 180 of file Gth7Core.vhd.

◆ txUsrClkIn

txUsrClkIn in sl
Port

Definition at line 181 of file Gth7Core.vhd.

◆ txUsrClk2In

txUsrClk2In in sl
Port

Definition at line 182 of file Gth7Core.vhd.

◆ txUserRdyOut

txUserRdyOut out sl
Port

Definition at line 183 of file Gth7Core.vhd.

◆ txMmcmResetOut

txMmcmResetOut out sl
Port

Definition at line 184 of file Gth7Core.vhd.

◆ txMmcmLockedIn

txMmcmLockedIn in sl := ' 1 '
Port

Definition at line 185 of file Gth7Core.vhd.

◆ txUserResetIn

txUserResetIn in sl
Port

Definition at line 187 of file Gth7Core.vhd.

◆ txResetDoneOut

txResetDoneOut out sl
Port

Definition at line 188 of file Gth7Core.vhd.

◆ txDataIn

txDataIn in slv ( TX_EXT_DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 190 of file Gth7Core.vhd.

◆ txCharIsKIn

txCharIsKIn in slv ( ( TX_EXT_DATA_WIDTH_G / 8 ) - 1 downto 0 )
Port

Definition at line 191 of file Gth7Core.vhd.

◆ txBufStatusOut

txBufStatusOut out slv ( 1 downto 0 )
Port

Definition at line 192 of file Gth7Core.vhd.

◆ txPolarityIn

txPolarityIn in sl := ' 0 '
Port

Definition at line 193 of file Gth7Core.vhd.

◆ txPowerDown

txPowerDown in slv ( 1 downto 0 ) := " 00 "
Port

Definition at line 195 of file Gth7Core.vhd.

◆ rxPowerDown

rxPowerDown in slv ( 1 downto 0 ) := " 00 "
Port

Definition at line 196 of file Gth7Core.vhd.

◆ loopbackIn

loopbackIn in slv ( 2 downto 0 ) := " 000 "
Port

Definition at line 197 of file Gth7Core.vhd.

◆ txPreCursor

txPreCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 198 of file Gth7Core.vhd.

◆ txPostCursor

txPostCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 199 of file Gth7Core.vhd.

◆ txDiffCtrl

txDiffCtrl in slv ( 3 downto 0 ) := " 1000 "
Port

Definition at line 200 of file Gth7Core.vhd.

◆ drpGnt

drpGnt out sl
Port

Definition at line 202 of file Gth7Core.vhd.

◆ drpRdy

drpRdy out sl
Port

Definition at line 203 of file Gth7Core.vhd.

◆ drpEn

drpEn in sl := ' 0 '
Port

Definition at line 204 of file Gth7Core.vhd.

◆ drpWe

drpWe in sl := ' 0 '
Port

Definition at line 205 of file Gth7Core.vhd.

◆ drpAddr

drpAddr in slv ( 8 downto 0 ) := " 000000000 "
Port

Definition at line 206 of file Gth7Core.vhd.

◆ drpDi

drpDi in slv ( 15 downto 0 ) := X " 0000 "
Port

Definition at line 207 of file Gth7Core.vhd.

◆ drpDo

drpDo out slv ( 15 downto 0 )
Port

Definition at line 208 of file Gth7Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file Gth7Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file Gth7Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file Gth7Core.vhd.

◆ unisim

unisim
Library

Definition at line 23 of file Gth7Core.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 24 of file Gth7Core.vhd.

The documentation for this class was generated from the following file: