XauiReg.rtl Architecture Reference

Architecture >> XauiReg::rtl

Processes
PROCESS_233	( localMacSync )
comb	( axiReadMaster , axiRst , axiWriteMaster , cntOut , localMacSync , r , statusOut )
seq	( axiClk )

Constants
STATUS_SIZE_C	positive := 32
REG_INIT_C	RegType := ( hardRst = > ' 0 ' , cntRst = > ' 1 ' , rollOverEn = > ( others = > ' 0 ' ) , config = > XAUI_CONFIG_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
statusOut	slv ( STATUS_SIZE_C- 1 downto 0 )
cntOut	SlVectorArray ( STATUS_SIZE_C- 1 downto 0 , 31 downto 0 )
localMacSync	slv ( 47 downto 0 )

Records
RegType

Instantiations
sync_config	SynchronizerVector <Entity SynchronizerVector>
sync_config	SynchronizerVector <Entity SynchronizerVector>
syncstatusvec_inst	SyncStatusVector <Entity SyncStatusVector>
syncin_macaddress	SynchronizerFifo <Entity SynchronizerFifo>
syncin_pausetime	SynchronizerFifo <Entity SynchronizerFifo>
syncin_macconfig	SynchronizerVector <Entity SynchronizerVector>
syncin_configvector	SynchronizerFifo <Entity SynchronizerFifo>
syncin_pausethresh	SynchronizerFifo <Entity SynchronizerFifo>

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The documentation for this design unit was generated from the following file:

• ethernet/XauiCore/core/rtl/XauiReg.vhd