UartWrapper.rtl Architecture Reference

Architecture >> UartWrapper::rtl

Signals
uartTxData	slv ( 7 downto 0 )
uartTxValid	sl
uartTxReady	sl
uartTxRdEn	sl
fifoTxData	slv ( 7 downto 0 )
fifoTxValid	sl
fifoTxReady	sl
uartRxData	slv ( 7 downto 0 )
uartRxValid	sl
uartRxValidInt	sl
uartRxReady	sl
fifoRxData	slv ( 7 downto 0 )
fifoRxValid	sl
fifoRxReady	sl
fifoRxRdEn	sl
baudClkEn	sl

Instantiations
u_uartbrg_1	UartBrg <Entity UartBrg>
u_uarttx_1	UartTx <Entity UartTx>
u_fifo_tx	Fifo <Entity Fifo>
u_uartrx_1	UartRx <Entity UartRx>
u_fifo_rx	Fifo <Entity Fifo>
u_uartbrg_1	UartBrg <Entity UartBrg>
u_uarttx_1	UartTx <Entity UartTx>
u_fifo_tx	Fifo <Entity Fifo>
u_uartrx_1	UartRx <Entity UartRx>
u_fifo_rx	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartWrapper.vhd
• protocols/uart/rtl/UartWrapper.vhd