UartBrg Entity Reference

Inheritance diagram for UartBrg:

Entities
UartBrg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
CLK_FREQ_G	real := 125 . 0E + 6
BAUD_RATE_G	integer := 115200
MULTIPLIER_G	integer := 16

Ports
clk	in	sl
rst	in	sl
baudClkEn	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartBrg.vhd
• protocols/uart/rtl/UartBrg.vhd