UartBrg.rtl Architecture Reference

Architecture >> UartBrg::rtl

Processes
comb	( r , rst )
seq	( clk )
comb	( r , rst )
seq	( clk )

Constants
CLK_DIV_C	integer := integer ( CLK_FREQ_G/ real ( BAUD_RATE_G* MULTIPLIER_G ) ) - 1
REG_INIT_C	RegType := ( count = > 0 , baudClkEn = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartBrg.vhd
• protocols/uart/rtl/UartBrg.vhd