UartAxiLiteMasterTb.sim Architecture Reference

Architecture >> UartAxiLiteMasterTb::sim

Functions
slv	hexStrToSlv ( s: in string )
slv	hexStrToSlv ( s: in string )

Processes
test
test

Procedures
	sendString( s: in string )
	receiveString( s: inout string )
	uartRegWrite( wrAddr: in slv ( 31 downto 0 ) , wrData: in slv ( 31 downto 0 ) )
	uartRegRead( rdAddr: in slv ( 31 downto 0 ) , rdData: inout slv ( 31 downto 0 ) )
	sendString( s: in string )
	receiveString( s: inout string )
	uartRegWrite( wrAddr: in slv ( 31 downto 0 ) , wrData: in slv ( 31 downto 0 ) )
	uartRegRead( rdAddr: in slv ( 31 downto 0 ) , rdData: inout slv ( 31 downto 0 ) )

Constants
TPD_G	time := 1 ns
CLK_FREQ_G	real := 125 . 0E + 6
BAUD_RATE_G	integer := 115200
MEMORY_TYPE_G	string := " distributed "
FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 5

Signals
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
tx	sl
rx	sl
clk	sl
rst	sl
wrData	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
wrValid	sl := ' 0 '
wrReady	sl
rdData	slv ( 7 downto 0 )
rdValid	sl
rdReady	sl := ' 1 '

Shared Variables
addr	slv ( 31 downto 0 )
data	slv ( 31 downto 0 )

Instantiations
u_clkrst_1	ClkRst <Entity ClkRst>
u_uartwrapper_1	UartWrapper <Entity UartWrapper>
u_uartaxilitemaster	UartAxiLiteMaster <Entity UartAxiLiteMaster>
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>
u_clkrst_1	ClkRst <Entity ClkRst>
u_uartwrapper_1	UartWrapper <Entity UartWrapper>
u_uartaxilitemaster	UartAxiLiteMaster <Entity UartAxiLiteMaster>
u_axidualportram_1	AxiDualPortRam <Entity AxiDualPortRam>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartAxiLiteMasterTb.vhd
• protocols/uart/sim/UartAxiLiteMasterTb.vhd