UartAxiLiteMaster Entity Reference

Inheritance diagram for UartAxiLiteMaster:

Collaboration diagram for UartAxiLiteMaster:

Entities
UartAxiLiteMaster.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
TextUtilPkg	Package <TextUtilPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
AXIL_CLK_FREQ_G	real := 125 . 0E + 6
BAUD_RATE_G	integer := 115200
STOP_BITS_G	integer range 1 to 2 := 1
PARITY_G	string := " NONE "
DATA_WIDTH_G	integer range 5 to 8 := 8
MEMORY_TYPE_G	string := " distributed "
FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 5

Ports
axilClk	in	sl
axilRst	in	sl
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType
mAxilReadMaster	out	AxiLiteReadMasterType
mAxilReadSlave	in	AxiLiteReadSlaveType
tx	out	sl
rx	in	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartAxiLiteMaster.vhd
• protocols/uart/rtl/UartAxiLiteMaster.vhd