UartAxiLiteMaster.mapping Architecture Reference

Architecture >> UartAxiLiteMaster::mapping

Signals
uartRxData	slv ( 7 downto 0 )
uartRxValid	sl
uartRxReady	sl
uartTxData	slv ( 7 downto 0 )
uartTxValid	sl
uartTxReady	sl

Instantiations
u_uartwrapper_1	UartWrapper <Entity UartWrapper>
u_fsm	UartAxiLiteMasterFsm <Entity UartAxiLiteMasterFsm>
u_uartwrapper_1	UartWrapper <Entity UartWrapper>
u_fsm	UartAxiLiteMasterFsm <Entity UartAxiLiteMasterFsm>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartAxiLiteMaster.vhd
• protocols/uart/rtl/UartAxiLiteMaster.vhd