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UartAxiLiteMasterFsm Entity Reference
Inheritance diagram for UartAxiLiteMasterFsm: Collaboration diagram for UartAxiLiteMasterFsm:Entities | |
| UartAxiLiteMasterFsm.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| TextUtilPkg | Package <TextUtilPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
Generics | |
| TPD_G | time := 1 ns |
Ports | ||
| axilClk | in | sl |
| axilRst | in | sl |
| uartTxValid | out | sl |
| uartTxData | out | slv ( 7 downto 0 ) |
| uartTxReady | in | sl |
| uartRxValid | in | sl |
| uartRxData | in | slv ( 7 downto 0 ) |
| uartRxReady | out | sl |
| mAxilWriteMaster | out | AxiLiteWriteMasterType |
| mAxilWriteSlave | in | AxiLiteWriteSlaveType |
| mAxilReadMaster | out | AxiLiteReadMasterType |
| mAxilReadSlave | in | AxiLiteReadSlaveType |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/UartAxiLiteMasterFsm.vhd
- protocols/uart/rtl/UartAxiLiteMasterFsm.vhd
