UartAxiLiteMasterFsm.rtl Architecture Reference

Architecture >> UartAxiLiteMasterFsm::rtl

Functions
slv	hexToSlv ( hex: in slv( 7 downto 0) )
slv	slvToHex ( nibble: in slv( 3 downto 0) )
boolean	isSpace ( byte: in slv( 7 downto 0) )
boolean	isEOL ( byte: in slv( 7 downto 0) )
slv	hexToSlv ( hex: in slv( 7 downto 0) )
slv	slvToHex ( nibble: in slv( 3 downto 0) )
boolean	isSpace ( byte: in slv( 7 downto 0) )
boolean	isEOL ( byte: in slv( 7 downto 0) )

Processes
comb	( axilAck , axilRst , r , uartRxData , uartRxValid , uartTxReady )
seq	( axilClk )
comb	( axilAck , axilRst , r , uartRxData , uartRxValid , uartTxReady )
seq	( axilClk )

Procedures
	uartTx( byte: in slv ( 7 downto 0 ) )
	uartTx( char: in character )
	uartTx( byte: in slv ( 7 downto 0 ) )
	uartTx( char: in character )

Constants
REG_INIT_C	RegType := ( state = > WAIT_START_S , count = > ( others = > ' 0 ' ) , axilReq = > AXI_LITE_REQ_INIT_C , rdData = > ( others = > ' 0 ' ) , uartTxData = > ( others = > ' 0 ' ) , uartTxValid = > ' 0 ' , uartRxReady = > ' 1 ' )

Types
StateType	( WAIT_START_S , SPACE_ADDR_S , ADDR_SPACE_S , WR_DATA_S , WAIT_EOL_S , AXIL_TXN_S , RD_DATA_SPACE_S , RD_DATA_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
axilAck	AxiLiteAckType

Records
RegType

Instantiations
u_axilitemaster_1	AxiLiteMaster <Entity AxiLiteMaster>
u_axilitemaster_1	AxiLiteMaster <Entity AxiLiteMaster>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/UartAxiLiteMasterFsm.vhd
• protocols/uart/rtl/UartAxiLiteMasterFsm.vhd