TenGigEthGtyUltraScale.mapping Architecture Reference

Architecture >> TenGigEthGtyUltraScale::mapping

Components
TenGigEthGtyUltraScale156p25MHzCore

Signals
mAxiReadMaster	AxiLiteReadMasterType
mAxiReadSlave	AxiLiteReadSlaveType
mAxiWriteMaster	AxiLiteWriteMasterType
mAxiWriteSlave	AxiLiteWriteSlaveType
phyRxd	slv ( 63 downto 0 )
phyRxc	slv ( 7 downto 0 )
phyTxd	slv ( 63 downto 0 )
phyTxc	slv ( 7 downto 0 )
txGtClk	sl
phyClock	sl
phyReset	sl
config	TenGigEthConfig
status	TenGigEthStatus
macRxAxisMaster	AxiStreamMasterType
macRxAxisCtrl	AxiStreamCtrlType
macTxAxisMaster	AxiStreamMasterType
macTxAxisSlave	AxiStreamSlaveType

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_mac	EthMacTop <Entity EthMacTop>
u_tengigethgtyultrascalecore	tengigethgtyultrascale156p25mhzcore
u_tengigethrst	TenGigEthGtyUltraScaleRst <Entity TenGigEthGtyUltraScaleRst>
u_tengigethreg	TenGigEthReg <Entity TenGigEthReg>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd