Architecture >> SrpV3CoreWrapper::rtl

Constants
TPD_C	time := 10 ns/ 4
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
CORE_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( CORE_DATA_BYTES_G )

Signals
axisRst	sl := ' 0 '
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rdAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rdAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
wrAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
wrAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
coreIbMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
coreIbSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
coreObMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
coreObSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
coreRdMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
coreRdSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
coreWrMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
coreWrSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
srpReq	SrpV3ReqType := SRPV3_REQ_INIT_C
srpAck	SrpV3AckType := SRPV3_ACK_INIT_C

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_readshim	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_writeshim	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_inputresize	AxiStreamResize <Entity AxiStreamResize>
u_outputresize	AxiStreamResize <Entity AxiStreamResize>
u_readresize	AxiStreamResize <Entity AxiStreamResize>
u_writeresize	AxiStreamResize <Entity AxiStreamResize>
u_dut	SrpV3Core <Entity SrpV3Core>

The documentation for this design unit was generated from the following file:

Constants

Signals