SrpV3CoreWrapper Entity Reference

Inheritance diagram for SrpV3CoreWrapper:

Collaboration diagram for SrpV3CoreWrapper:

Entities
SrpV3CoreWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
SrpV3Pkg	Package <SrpV3Pkg>

Generics
CORE_DATA_BYTES_G	positive range 4 to 64 := 8
WRITE_EN_G	boolean := true
READ_EN_G	boolean := true

Ports
AXIS_ACLK	in	std_logic
AXIS_ARESETN	in	std_logic
S_AXIS_TVALID	in	std_logic
S_AXIS_TDATA	in	std_logic_vector ( 31 downto 0 )
S_AXIS_TKEEP	in	std_logic_vector ( 3 downto 0 )
S_AXIS_TLAST	in	std_logic
S_AXIS_TDEST	in	std_logic_vector ( 3 downto 0 )
S_AXIS_TID	in	std_logic_vector ( 0 downto 0 )
S_AXIS_TUSER	in	std_logic_vector ( 1 downto 0 )
S_AXIS_TREADY	out	std_logic
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( 31 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( 3 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( 3 downto 0 )
M_AXIS_TID	out	std_logic_vector ( 0 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( 1 downto 0 )
M_AXIS_TREADY	in	std_logic
RD_AXIS_TVALID	in	std_logic
RD_AXIS_TDATA	in	std_logic_vector ( 31 downto 0 )
RD_AXIS_TKEEP	in	std_logic_vector ( 3 downto 0 )
RD_AXIS_TLAST	in	std_logic
RD_AXIS_TUSER	in	std_logic_vector ( 1 downto 0 )
RD_AXIS_TREADY	out	std_logic
WR_AXIS_TVALID	out	std_logic
WR_AXIS_TDATA	out	std_logic_vector ( 31 downto 0 )
WR_AXIS_TKEEP	out	std_logic_vector ( 3 downto 0 )
WR_AXIS_TLAST	out	std_logic
WR_AXIS_TUSER	out	std_logic_vector ( 1 downto 0 )
WR_AXIS_TREADY	in	std_logic
SRP_REQ_REQUEST	out	std_logic
SRP_REQ_REM_VER	out	std_logic_vector ( 7 downto 0 )
SRP_REQ_OPCODE	out	std_logic_vector ( 1 downto 0 )
SRP_REQ_PROT	out	std_logic_vector ( 2 downto 0 )
SRP_REQ_TID	out	std_logic_vector ( 31 downto 0 )
SRP_REQ_ADDR	out	std_logic_vector ( 63 downto 0 )
SRP_REQ_REQ_SIZE	out	std_logic_vector ( 31 downto 0 )
SRP_ACK_DONE	in	std_logic
SRP_ACK_RESP	in	std_logic_vector ( 7 downto 0 )

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The documentation for this design unit was generated from the following file:

• protocols/srp/wrappers/SrpV3CoreWrapper.vhd