Architecture >> SrpV3AxiLiteTb::tb

Processes
comb	( mAxisMaster , r , rst , sAxisSlave )
seq	( clk )
comb	( mAxisMaster , r , rst , sAxisSlave )
seq	( clk )

Constants
GET_BUILD_INFO_C	BuildInfoRetType := toBuildInfo ( BUILD_INFO_C )
MOD_BUILD_INFO_C	BuildInfoRetType := ( buildString = > GET_BUILD_INFO_C.buildString , fwVersion = > x " 1234_5678 " , gitHash = > x " 1111_2222_3333_4444_5555_6666_7777_8888_9999_AAAA " )
SIM_BUILD_INFO_C	slv ( 2239 downto 0 ) := toSlv ( MOD_BUILD_INFO_C )
CLK_PERIOD_C	time := 10 ns
TPD_G	time := CLK_PERIOD_C/ 4
MAX_TID_C	natural := 3
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 32 )
NUM_AXIL_MASTERS_C	natural := 1
VERSION_INDEX_C	natural := 0
AXIL_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , x " 0000_0000 " , 16 , 12 )
REG_INIT_C	RegType := ( tid = > ( others = > ' 0 ' ) , sAxisMaster = > AXI_STREAM_MASTER_INIT_C , mAxisSlave = > AXI_STREAM_SLAVE_INIT_C , state = > REQ_S )

Types
StateType	( REQ_S , RESP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl := ' 0 '
rst	sl := ' 1 '
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_srpv3	SrpV3AxiLite <Entity SrpV3AxiLite>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axiversion	AxiVersion <Entity AxiVersion>
u_clkrst	ClkRst <Entity ClkRst>
u_srpv3	SrpV3AxiLite <Entity SrpV3AxiLite>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axiversion	AxiVersion <Entity AxiVersion>

The documentation for this design unit was generated from the following files:

Processes

Constants