SaltCoreTb.testbed Architecture Reference

Architecture >> SaltCoreTb::testbed

Processes
PROCESS_360	( mps125MHzClk )
PROCESS_361	( failed , passed )

Constants
TPD_G	time := 0 . 6 ns
TX_PACKET_LENGTH_C	slv ( 31 downto 0 ) := toSlv ( 256 , 32 )
NUMBER_PACKET_C	slv ( 31 downto 0 ) := x " 000000FF "
PRBS_SEED_SIZE_C	positive := 8 * SSI_SALT_CONFIG_C.TDATA_BYTES_C

Signals
txMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
rxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
linkUp	sl := ' 0 '
passed	sl := ' 0 '
failed	sl := ' 0 '
updated	sl := ' 0 '
errorDet	sl := ' 0 '
cnt	slv ( 31 downto 0 )
mps125MHzClk	sl := ' 0 '
mps125MHzRst	sl := ' 1 '
mps156MHzClk	sl := ' 0 '
mps156MHzRst	sl := ' 1 '
mps625MHzClkP	sl := ' 0 '
mps625MHzClkN	sl := ' 1 '
mps625MHzRst	sl := ' 1 '
loopbackP	sl := ' 0 '
loopbackN	sl := ' 1 '

Instantiations
u_125mhz	ClkRst <Entity ClkRst>
u_156mhz	ClkRst <Entity ClkRst>
u_625mhz	ClkRst <Entity ClkRst>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_dut	SaltCore <Entity SaltCore>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>

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The documentation for this design unit was generated from the following file:

• protocols/salt/tb/SaltCoreTb.vhd