SaltCore Entity Reference

Inheritance diagram for SaltCore:

Collaboration diagram for SaltCore:

Entities
SaltCore.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
SIM_DEVICE_G	string := " ULTRASCALE "
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true
COMMON_TX_CLK_G	boolean := false
COMMON_RX_CLK_G	boolean := false
IODELAY_GROUP_G	string := " SALT_GROUP "
REF_FREQ_G	real := 200 . 0
SLAVE_AXI_CONFIG_G	AxiStreamConfigType
MASTER_AXI_CONFIG_G	AxiStreamConfigType

Ports
txP	out	sl
txN	out	sl
rxP	in	sl
rxN	in	sl
clk125MHz	in	sl
rst125MHz	in	sl
clk156MHz	in	sl
rst156MHz	in	sl
clk625MHz	in	sl
linkUp	out	sl
txPktSent	out	sl
txEofeSent	out	sl
rxPktRcvd	out	sl
rxErrDet	out	sl
enUsrDlyCfg	in	sl := ' 0 '
usrDlyCfg	in	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
bypFirstBerDet	in	sl := ' 1 '
minEyeWidth	in	slv ( 7 downto 0 ) := toSlv ( 80 , 8 )
lockingCntCfg	in	slv ( 23 downto 0 ) := ite ( SIMULATION_G , x " 00_0064 " , x " 00_FFFF " )
sAxisClk	in	sl
sAxisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

---

The documentation for this design unit was generated from the following file:

• protocols/salt/rtl/SaltCore.vhd