SaciAxiLiteMasterTb.mapping Architecture Reference

Architecture >> SaciAxiLiteMasterTb::mapping

Signals
fpgaAxilClk	sl
fpgaAxilRst	sl
fpgaAxilReadMaster	AxiLiteReadMasterType
fpgaAxilReadSlave	AxiLiteReadSlaveType
fpgaAxilWriteMaster	AxiLiteWriteMasterType
fpgaAxilWriteSlave	AxiLiteWriteSlaveType
asicAxilClk	sl
asicAxilRst	sl
asicAxilReadMaster	AxiLiteReadMasterType
asicAxilReadSlave	AxiLiteReadSlaveType
asicAxilWriteMaster	AxiLiteWriteMasterType
asicAxilWriteSlave	AxiLiteWriteSlaveType
rstL	sl
saciClk	sl
saciCmd	sl
saciSelL	slv ( 0 downto 0 )
saciRsp	slv ( 0 downto 0 )
saciBusReq	sl
saciBusGr	sl := ' 1 '

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axilitesacimaster_1	AxiLiteSaciMaster <Entity AxiLiteSaciMaster>
u_clkrst_1	ClkRst <Entity ClkRst>
u_saciaxilitemaster_1	SaciAxiLiteMaster <Entity SaciAxiLiteMaster>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_axilitesacimaster_1	AxiLiteSaciMaster <Entity AxiLiteSaciMaster>
u_clkrst_1	ClkRst <Entity ClkRst>
u_saciaxilitemaster_1	SaciAxiLiteMaster <Entity SaciAxiLiteMaster>
u_mem	AxiDualPortRam <Entity AxiDualPortRam>

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciAxiLiteMasterTb.vhd
• protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd