RssiInterleaveTb.testbed Architecture Reference

Architecture >> RssiInterleaveTb::testbed

Processes
PROCESS_147	( clk )
PROCESS_148	( failed , passed )
PROCESS_357	( clk )
PROCESS_358	( failed , passed )

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := CLK_PERIOD_C/ 4
PRBS_SEED_SIZE_C	positive := 128
SRV_PKT_LEN_C	slv ( 31 downto 0 ) := x " 00000007 "
SRV_WINDOW_ADDR_SIZE_C	positive := 4
SRV_MAX_SEG_SIZE_C	positive := 8192
CLT_PKT_LEN_C	slv ( 31 downto 0 ) := x " 00000003 "
CLT_WINDOW_ADDR_SIZE_C	positive := 3
CLT_MAX_SEG_SIZE_C	positive := 1024
APP_STREAMS_C	positive := 5
SRV_AXIS_CONFIG_C	AxiStreamConfigArray ( APP_STREAMS_C- 1 downto 0 ) := ( 0 = > ssiAxiStreamConfig ( 1 ) , 1 = > ssiAxiStreamConfig ( 2 ) , 2 = > ssiAxiStreamConfig ( 4 ) , 3 = > ssiAxiStreamConfig ( 8 ) , 4 = > ssiAxiStreamConfig ( 16 ) )
CLT_AXIS_CONFIG_C	AxiStreamConfigArray ( APP_STREAMS_C- 1 downto 0 ) := ( 0 = > ssiAxiStreamConfig ( 16 ) , 1 = > ssiAxiStreamConfig ( 8 ) , 2 = > ssiAxiStreamConfig ( 4 ) , 3 = > ssiAxiStreamConfig ( 2 ) , 4 = > ssiAxiStreamConfig ( 1 ) )

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
linkUp	slv ( 1 downto 0 ) := " 00 "
tspMasters	AxiStreamMasterArray ( 1 downto 0 )
tspSlaves	AxiStreamSlaveArray ( 1 downto 0 )
srvIbMasters	AxiStreamMasterArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
srvIbSlaves	AxiStreamSlaveArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
srvObMasters	AxiStreamMasterArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
srvObSlaves	AxiStreamSlaveArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
srvUpdateDet	slv ( APP_STREAMS_C- 1 downto 0 )
srvErrorDet	slv ( APP_STREAMS_C- 1 downto 0 )
cltIbMasters	AxiStreamMasterArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
cltIbSlaves	AxiStreamSlaveArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
cltObMasters	AxiStreamMasterArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
cltObSlaves	AxiStreamSlaveArray ( APP_STREAMS_C- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
cltUpdateDet	slv ( APP_STREAMS_C- 1 downto 0 )
cltErrorDet	slv ( APP_STREAMS_C- 1 downto 0 )
passed	sl := ' 0 '
failed	sl := ' 0 '

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>
u_rssiserver	RssiCoreWrapper <Entity RssiCoreWrapper>
u_rssiclient	RssiCoreWrapper <Entity RssiCoreWrapper>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>
u_clkrst	ClkRst <Entity ClkRst>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>
u_rssiserver	RssiCoreWrapper <Entity RssiCoreWrapper>
u_rssiclient	RssiCoreWrapper <Entity RssiCoreWrapper>
u_ssiprbstx	SsiPrbsTx <Entity SsiPrbsTx>
u_ssiprbsrx	SsiPrbsRx <Entity SsiPrbsRx>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiInterleaveTb.vhd
• protocols/rssi/v1/tb/RssiInterleaveTb.vhd