RssiCoreWrapper Entity Reference

Inheritance diagram for RssiCoreWrapper:

Collaboration diagram for RssiCoreWrapper:

Entities
RssiCoreWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
RssiPkg	Package <RssiPkg>
SsiPkg	Package <SsiPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
CLK_FREQUENCY_G	real := 156 . 25E + 6
TIMEOUT_UNIT_G	real := 1 . 0E - 3
SERVER_G	boolean := true
RETRANSMIT_ENABLE_G	boolean := true
WINDOW_ADDR_SIZE_G	positive := 3
SEGMENT_ADDR_SIZE_G	positive := 7
BYPASS_CHUNKER_G	boolean := false
PIPE_STAGES_G	natural := 0
APP_STREAMS_G	positive := 1
APP_STREAM_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
APP_STREAM_PRIORITY_G	IntegerArray := ( 0 = > 0 )
APP_ILEAVE_EN_G	boolean := false
BYP_TX_BUFFER_G	boolean := false
BYP_RX_BUFFER_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
ILEAVE_ON_NOTVALID_G	boolean := false
APP_AXIS_CONFIG_G	AxiStreamConfigArray
TSP_AXIS_CONFIG_G	AxiStreamConfigType
INIT_SEQ_N_G	natural := 16#80#
CONN_ID_G	positive := 16#12345678#
VERSION_G	positive := 1
HEADER_CHKSUM_EN_G	boolean := true
MAX_NUM_OUTS_SEG_G	positive := 8
MAX_SEG_SIZE_G	positive := 1024
ACK_TOUT_G	positive := 25
RETRANS_TOUT_G	positive := 50
NULL_TOUT_G	positive := 200
MAX_RETRANS_CNT_G	positive := 2
MAX_CUM_ACK_CNT_G	positive := 3

Ports
clk_i	in	sl
rst_i	in	sl
sAppAxisMasters_i	in	AxiStreamMasterArray ( APP_STREAMS_G- 1 downto 0 )
sAppAxisSlaves_o	out	AxiStreamSlaveArray ( APP_STREAMS_G- 1 downto 0 )
mAppAxisMasters_o	out	AxiStreamMasterArray ( APP_STREAMS_G- 1 downto 0 )
mAppAxisSlaves_i	in	AxiStreamSlaveArray ( APP_STREAMS_G- 1 downto 0 )
sTspAxisMaster_i	in	AxiStreamMasterType
sTspAxisSlave_o	out	AxiStreamSlaveType
mTspAxisMaster_o	out	AxiStreamMasterType
mTspAxisSlave_i	in	AxiStreamSlaveType
openRq_i	in	sl := ' 0 '
closeRq_i	in	sl := ' 0 '
inject_i	in	sl := ' 0 '
rssiConnected_o	out	sl
axiClk_i	in	sl := ' 0 '
axiRst_i	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
statusReg_o	out	slv ( 8 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiCoreWrapper.vhd
• protocols/rssi/v1/rtl/RssiCoreWrapper.vhd