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RssiCoreTb.testbed Architecture Reference
Architecture >> RssiCoreTb::testbed

Processes

comb  ( r , rst , statusReg , txSlave )
seq  ( clk )
comb  ( r , rst , statusReg , txSlave )
seq  ( clk )

Constants

CLK_PERIOD_C  time := 10 ns
TPD_G  time := CLK_PERIOD_C/ 4
AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
AXIL_CONFIG_C  AxiLiteCrossbarMasterConfigArray ( 0 downto 0 ) := ( 0 = > ( baseAddr = > x " 0000_0000 " , addrBits = > 32 , connectivity = > x " FFFF " ) )
MAX_CNT_C  positive := ( 4096 / 4 )
SWEEP_C  boolean := true
APP_ILEAVE_EN_C  boolean := true
REG_INIT_C  RegType := ( tid = > x " 0000_0000 " , cnt = > x " 0000_0000 " , sweep = > x " 0000_0000 " , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )
NUM_XBAR_C  positive := 8

Types

StateType  ( IDLE_S , HDR0_S , HDR1_S , HDR2_S , HDR3_S , HDR4_S , PAYLOAD_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
clk  sl := ' 0 '
rst  sl := ' 0 '
axilWriteMasters  AxiLiteWriteMasterArray ( NUM_XBAR_C- 1 downto 0 )
axilWriteSlaves  AxiLiteWriteSlaveArray ( NUM_XBAR_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_OK_C )
axilReadMasters  AxiLiteReadMasterArray ( NUM_XBAR_C- 1 downto 0 )
axilReadSlaves  AxiLiteReadSlaveArray ( NUM_XBAR_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_OK_C )
sSrpMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sSrpSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mSrpMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mSrpSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
tspMasters  AxiStreamMasterArray ( 1 downto 0 )
tspSlaves  AxiStreamSlaveArray ( 1 downto 0 )
txMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rxMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
statusReg  slv ( 8 downto 0 )

Records

RegType 

Instantiations

u_clkrst  ClkRst <Entity ClkRst>
u_xbar  AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_srpv3  SrpV3AxiLite <Entity SrpV3AxiLite>
u_rssiserver  RssiCoreWrapper <Entity RssiCoreWrapper>
u_rssiclient  RssiCoreWrapper <Entity RssiCoreWrapper>
u_clkrst  ClkRst <Entity ClkRst>
u_xbar  AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_srpv3  SrpV3AxiLite <Entity SrpV3AxiLite>
u_rssiserver  RssiCoreWrapper <Entity RssiCoreWrapper>
u_rssiclient  RssiCoreWrapper <Entity RssiCoreWrapper>

The documentation for this design unit was generated from the following files: