Architecture >> RssiCoreTb::testbed
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comb | ( r , rst , statusReg , txSlave ) |
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seq | ( clk ) |
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comb | ( r , rst , statusReg , txSlave ) |
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seq | ( clk ) |
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CLK_PERIOD_C | time := 10 ns |
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TPD_G | time := CLK_PERIOD_C/ 4 |
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AXIS_CONFIG_C | AxiStreamConfigType := ssiAxiStreamConfig ( 4 ) |
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AXIL_CONFIG_C | AxiLiteCrossbarMasterConfigArray ( 0 downto 0 ) := ( 0 = > ( baseAddr = > x " 0000_0000 " , addrBits = > 32 , connectivity = > x " FFFF " ) ) |
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MAX_CNT_C | positive := ( 4096 / 4 ) |
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SWEEP_C | boolean := true |
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APP_ILEAVE_EN_C | boolean := true |
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REG_INIT_C | RegType := ( tid = > x " 0000_0000 " , cnt = > x " 0000_0000 " , sweep = > x " 0000_0000 " , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S ) |
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NUM_XBAR_C | positive := 8 |
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StateType | ( IDLE_S , HDR0_S , HDR1_S , HDR2_S , HDR3_S , HDR4_S , PAYLOAD_S ) |
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r | RegType := REG_INIT_C |
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rin | RegType |
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clk | sl := ' 0 ' |
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rst | sl := ' 0 ' |
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axilWriteMasters | AxiLiteWriteMasterArray ( NUM_XBAR_C- 1 downto 0 ) |
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axilWriteSlaves | AxiLiteWriteSlaveArray ( NUM_XBAR_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_OK_C ) |
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axilReadMasters | AxiLiteReadMasterArray ( NUM_XBAR_C- 1 downto 0 ) |
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axilReadSlaves | AxiLiteReadSlaveArray ( NUM_XBAR_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_OK_C ) |
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sSrpMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
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sSrpSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C |
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mSrpMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
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mSrpSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C |
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tspMasters | AxiStreamMasterArray ( 1 downto 0 ) |
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tspSlaves | AxiStreamSlaveArray ( 1 downto 0 ) |
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txMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
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txSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C |
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rxMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
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rxSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C |
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statusReg | slv ( 8 downto 0 ) |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/RssiCoreTb.vhd
- protocols/rssi/v1/tb/RssiCoreTb.vhd