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Pgp4Tb.tb Architecture Reference
Architecture >> Pgp4Tb::tb

Processes

PROCESS_142 
PROCESS_353 

Constants

TPD_G  time := 1 ns
TX_CELL_WORDS_MAX_G  integer := PGP4_DEFAULT_TX_CELL_WORDS_MAX_C
NUM_VC_G  integer := 4
SKP_INTERVAL_G  integer := 5000
SKP_BURST_SIZE_G  integer := 8
MUX_MODE_G  string := " INDEXED "
MUX_TDEST_ROUTES_G  Slv8Array := ( 0 = > " -------- " )
MUX_TDEST_LOW_G  integer range 0 to 7 := 0
MUX_INTERLEAVE_EN_G  boolean := true
MUX_INTERLEAVE_ON_NOTVALID_G  boolean := false
PACKETIZER_IN_AXIS_CFG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
RX_AXIS_CFG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )

Signals

rxClk  sl
rxRst  sl
axisClk  sl
axisRst  sl
pgpTxIn  Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOut  Pgp4TxOutType
pgpTxMasters  AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves  AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
locRxLinkReady  sl
remRxFifoCtrl  AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
remRxLinkReady  sl
phyTxData  slv ( 63 downto 0 )
phyTxHeader  slv ( 1 downto 0 )
phyRxData  slv ( 63 downto 0 )
phyRxHeader  slv ( 1 downto 0 )
pgpRxIn  Pgp4RxInType := PGP4_RX_IN_INIT_C
pgpRxOut  Pgp4RxOutType
pgpRxMasters  AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpRxCtrl  AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )

Instantiations

u_clkrst_1  ClkRst <Entity ClkRst>
u_ssiprbstx_1  SsiPrbsTx <Entity SsiPrbsTx>
u_pgp4tx_1  Pgp4Tx <Entity Pgp4Tx>
u_pgp4rx_1  Pgp4Rx <Entity Pgp4Rx>
u_clkrst_2  ClkRst <Entity ClkRst>
u_axistreamfifov2_1  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_clkrst_1  ClkRst <Entity ClkRst>
u_ssiprbstx_1  SsiPrbsTx <Entity SsiPrbsTx>
u_pgp4tx_1  Pgp4Tx <Entity Pgp4Tx>
u_pgp4rx_1  Pgp4Rx <Entity Pgp4Rx>
u_clkrst_2  ClkRst <Entity ClkRst>
u_axistreamfifov2_1  AxiStreamFifoV2 <Entity AxiStreamFifoV2>

The documentation for this design unit was generated from the following files: