Architecture >> Pgp4LiteRxLowSpeed::mapping

Constants
NUM_AXIL_MASTERS_C	positive := NUM_LANE_G+ 1
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 20 , 12 )

Signals
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C )
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C )
deserReset	sl
dlyConfig	Slv9Array ( NUM_LANE_G- 1 downto 0 )
enUsrDlyCfg	sl
usrDlyCfg	Slv9Array ( NUM_LANE_G- 1 downto 0 )
minEyeWidth	slv ( 7 downto 0 )
lockingCntCfg	slv ( 23 downto 0 )
bypFirstBerDet	sl
polarity	slv ( NUM_LANE_G- 1 downto 0 )
bitOrder	slv ( 1 downto 0 )
errorDet	slv ( NUM_LANE_G- 1 downto 0 )
bitSlip	slv ( NUM_LANE_G- 1 downto 0 )
eyeWidth	Slv9Array ( NUM_LANE_G- 1 downto 0 )
locked	slv ( NUM_LANE_G- 1 downto 0 )

Instantiations
u_deserreset	RstPipeline <Entity RstPipeline>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_reg	Pgp4RxLiteLowSpeedReg <Entity Pgp4RxLiteLowSpeedReg>
u_pgplane	Pgp4RxLiteLowSpeedLane <Entity Pgp4RxLiteLowSpeedLane>

The documentation for this design unit was generated from the following file:

Constants

Signals