Pgp4RxLiteLowSpeedReg Entity Reference

Inheritance diagram for Pgp4RxLiteLowSpeedReg:

Collaboration diagram for Pgp4RxLiteLowSpeedReg:

Entities
Pgp4RxLiteLowSpeedReg.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
NUM_LANE_G	positive := 1

Ports
deserClk	in	sl
deserRst	in	sl
dlyConfig	in	Slv9Array ( NUM_LANE_G- 1 downto 0 )
errorDet	in	slv ( NUM_LANE_G- 1 downto 0 )
bitSlip	in	slv ( NUM_LANE_G- 1 downto 0 )
eyeWidth	in	Slv9Array ( NUM_LANE_G- 1 downto 0 )
locked	in	slv ( NUM_LANE_G- 1 downto 0 )
enUsrDlyCfg	out	sl
usrDlyCfg	out	Slv9Array ( NUM_LANE_G- 1 downto 0 )
minEyeWidth	out	slv ( 7 downto 0 )
lockingCntCfg	out	slv ( 23 downto 0 )
bypFirstBerDet	out	sl
polarity	out	slv ( NUM_LANE_G- 1 downto 0 )
bitOrder	out	slv ( 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4RxLiteLowSpeedReg.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedReg.vhd