Pgp4RxLiteLowSpeedLane Entity Reference

Inheritance diagram for Pgp4RxLiteLowSpeedLane:

Collaboration diagram for Pgp4RxLiteLowSpeedLane:

Entities
Pgp4RxLiteLowSpeedLane.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
DLY_STEP_SIZE_G	positive range 1 to 255 := 1
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 32 := 8
AXIL_CLK_FREQ_G	real

Ports
deserClk	in	sl
deserRst	in	sl
deserData	in	slv ( 7 downto 0 )
dlyLoad	out	sl
dlyCfg	out	slv ( 8 downto 0 )
enUsrDlyCfg	in	sl
usrDlyCfg	in	slv ( 8 downto 0 )
minEyeWidth	in	slv ( 7 downto 0 )
lockingCntCfg	in	slv ( 23 downto 0 )
bypFirstBerDet	in	sl
polarity	in	sl
bitOrder	in	slv ( 1 downto 0 )
errorDet	out	sl
bitSlip	out	sl
eyeWidth	out	slv ( 8 downto 0 )
locked	out	sl
pgpRxMaster	out	AxiStreamMasterType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4RxLiteLowSpeedLane.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd