Pgp4RxLiteLowSpeedLane.mapping Architecture Reference

Architecture >> Pgp4RxLiteLowSpeedLane::mapping

Processes
PROCESS_141	( deserClk )
PROCESS_350	( deserClk )

Signals
deserDataMask	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
deserReset	sl := ' 1 '
gearboxAligned	sl := ' 0 '
slip	sl := ' 0 '
phyRxValid	sl := ' 0 '
phyRxData	slv ( 65 downto 0 )
phyRxValidMask	sl := ' 0 '

Instantiations
u_reset	RstPipeline <Entity RstPipeline>
u_gearbox	Gearbox <Entity Gearbox>
u_gearboxaligner	SelectIoRxGearboxAligner <Entity SelectIoRxGearboxAligner>
u_pgp4corelite	Pgp4CoreLite <Entity Pgp4CoreLite>
u_reset	RstPipeline <Entity RstPipeline>
u_gearbox	Gearbox <Entity Gearbox>
u_gearboxaligner	SelectIoRxGearboxAligner <Entity SelectIoRxGearboxAligner>
u_pgp4corelite	Pgp4CoreLite <Entity Pgp4CoreLite>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4RxLiteLowSpeedLane.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd