Architecture >> Pgp4Gtp7Wrapper::rtl

Constants
CLKIN_PERIOD_C	real := ite ( ( RATE_G = " 6.25Gbps " ) , 2 . 56 , 5 . 12 )
BANDWIDTH_C	string := ite ( ( SPEED_GRADE_G = 3 ) , " HIGH " , " OPTIMIZED " )
CLKFBOUT_MULT_C	positive := ite ( ( SPEED_GRADE_G = 3 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 4 , 8 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 3 , 6 ) )
CLKOUT0_DIVIDE_C	positive := ite ( ( SPEED_GRADE_G = 3 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 16 , 32 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 12 , 24 ) )
CLKOUT1_DIVIDE_C	positive := ite ( ( SPEED_GRADE_G = 3 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 4 , 8 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 3 , 6 ) )
CLKOUT2_DIVIDE_C	positive := ite ( ( SPEED_GRADE_G = 3 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 8 , 16 ) , ite ( ( RATE_G = " 6.25Gbps " ) , 6 , 12 ) )
NUM_AXIL_MASTERS_C	integer := NUM_LANES_G+ 1
QPLL_AXIL_INDEX_C	integer := NUM_AXIL_MASTERS_C- 1
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 16 , 13 )

Signals
qPllOutClk	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
qPllOutRefClk	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
qPllLock	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
qPllRefClkLost	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
qpllRst	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
gtTxOutClk	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
gtTxPllRst	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
gtTxPllLock	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
pllOut	slv ( 2 downto 0 ) := ( others = > ' 0 ' )
txPllClk	slv ( 2 downto 0 ) := ( others = > ' 0 ' )
txPllRst	slv ( 2 downto 0 ) := ( others = > ' 0 ' )
lockedStrobe	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
pllLock	sl
pgpRefClkDiv2	sl
pgpRefClk	sl
clkFb	sl
gtTxOutClkBufg	sl
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )

Instantiations
u_bufg	bufg
u_pgprefclk	ibufds_gte2
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_qpll	Pgp3Gtp7Qpll <Entity Pgp3Gtp7Qpll>
u_pgp	Pgp4Gtp7 <Entity Pgp4Gtp7>
u_pwruprst	PwrUpRst <Entity PwrUpRst>
u_bufg	bufh
u_tx_pll	plle2_adv
u_txpllclk0	bufg
u_txpllclk1	bufg
u_txpllclk2	bufg
u_rstsync	RstSync <Entity RstSync>
u_rogue	RoguePgp4Sim <Entity RoguePgp4Sim>

The documentation for this design unit was generated from the following file:

Constants

Signals