Pgp4Gtp7 Entity Reference

Inheritance diagram for Pgp4Gtp7:

Collaboration diagram for Pgp4Gtp7:

Entities
Pgp4Gtp7.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp4Pkg	Package <Pgp4Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
RATE_G	string := " 6.25Gbps "
CLKIN_PERIOD_G	real
BANDWIDTH_G	string
CLKFBOUT_MULT_G	positive
CLKOUT0_DIVIDE_G	positive
CLKOUT1_DIVIDE_G	positive
CLKOUT2_DIVIDE_G	positive
PGP_RX_ENABLE_G	boolean := true
RX_ALIGN_SLIP_WAIT_G	integer := 32
PGP_TX_ENABLE_G	boolean := true
NUM_VC_G	integer range 1 to 16 := 4
TX_CELL_WORDS_MAX_G	integer := PGP4_DEFAULT_TX_CELL_WORDS_MAX_C
TX_MUX_MODE_G	string := " INDEXED "
TX_MUX_TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TX_MUX_TDEST_LOW_G	integer range 0 to 7 := 0
TX_MUX_ILEAVE_EN_G	boolean := true
TX_MUX_ILEAVE_ON_NOTVALID_G	boolean := true
EN_DRP_G	boolean := false
EN_PGP_MON_G	boolean := false
WRITE_EN_G	boolean := true
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 32 := 8
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXIL_CLK_FREQ_G	real := 156 . 25E + 6

Ports
stableClk	in	sl
stableRst	in	sl
qPllOutClk	in	slv ( 1 downto 0 )
qPllOutRefClk	in	slv ( 1 downto 0 )
qPllLock	in	slv ( 1 downto 0 )
qPllRefClkLost	in	slv ( 1 downto 0 )
qpllRst	out	slv ( 1 downto 0 )
gtTxOutClk	out	sl
gtTxPllRst	out	sl
txPllClk	in	slv ( 2 downto 0 )
txPllRst	in	slv ( 2 downto 0 )
gtTxPllLock	in	sl
pgpGtTxP	out	sl
pgpGtTxN	out	sl
pgpGtRxP	in	sl
pgpGtRxN	in	sl
pgpClk	out	sl
pgpClkRst	out	sl
pgpRxIn	in	Pgp4RxInType := PGP4_RX_IN_INIT_C
pgpRxOut	out	Pgp4RxOutType
pgpTxIn	in	Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOut	out	Pgp4TxOutType
pgpTxMasters	in	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpRxCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd