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Pgp3Gtp7Qpll Entity Reference
Inheritance diagram for Pgp3Gtp7Qpll: Collaboration diagram for Pgp3Gtp7Qpll:Entities | |
| Pgp3Gtp7Qpll.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| Pgp3Pkg | Package <Pgp3Pkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| EN_DRP_G | boolean := true |
| REFCLK_FREQ_G | real := 250 . 0E + 6 |
| RATE_G | string := " 6.25Gbps " |
Ports | ||
| stableClk | in | sl |
| stableRst | in | sl |
| pgpRefClk | in | sl |
| qPllOutClk | out | Slv2Array ( 3 downto 0 ) |
| qPllOutRefClk | out | Slv2Array ( 3 downto 0 ) |
| qPllLock | out | Slv2Array ( 3 downto 0 ) |
| qPllRefClkLost | out | Slv2Array ( 3 downto 0 ) |
| qpllRst | in | Slv2Array ( 3 downto 0 ) |
| axilClk | in | sl := ' 0 ' |
| axilRst | in | sl := ' 0 ' |
| axilReadMaster | in | AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C |
| axilReadSlave | out | AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C |
| axilWriteMaster | in | AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C |
| axilWriteSlave | out | AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C |
The documentation for this design unit was generated from the following file:
- protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd
