Pgp4CoreTb.testbed Architecture Reference

Architecture >> Pgp4CoreTb::testbed

Constants
TUSER_WIDTH_C	positive := 1
TID_WIDTH_C	positive := 1
TDEST_WIDTH_C	positive := 1
TDATA_NUM_BYTES_C	positive := 8

Signals
axisClk	sl := ' 0 '
axisRst	sl := ' 0 '
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
pgpTxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
pgpTxSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
pgpTxIn	Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOut	Pgp4TxOutType
phyValid	sl := ' 0 '
phyData	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyHeader	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
pgpRxIn	Pgp4RxInType := PGP4_RX_IN_INIT_C
pgpRxOut	Pgp4RxOutType
pgpRxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
pgpRxCtrl	AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_insertsof	SsiInsertSof <Entity SsiInsertSof>
u_dut	Pgp4Core <Entity Pgp4Core>
u_rxfifo	PgpRxVcFifo <Entity PgpRxVcFifo>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/core/tb/Pgp4CoreTb.vhd