Pgp4Core Entity Reference

Inheritance diagram for Pgp4Core:

Collaboration diagram for Pgp4Core:

Entities
Pgp4Core.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
NUM_VC_G	integer range 1 to 16 := 4
PGP_FEC_ENABLE_G	boolean := false
PGP_RX_ENABLE_G	boolean := true
RX_ALIGN_SLIP_WAIT_G	integer := 32
PGP_TX_ENABLE_G	boolean := true
TX_CELL_WORDS_MAX_G	integer := PGP4_DEFAULT_TX_CELL_WORDS_MAX_C
TX_MUX_MODE_G	string := " INDEXED "
TX_MUX_TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TX_MUX_TDEST_LOW_G	integer range 0 to 7 := 0
TX_MUX_ILEAVE_EN_G	boolean := true
TX_MUX_ILEAVE_ON_NOTVALID_G	boolean := true
EN_PGP_MON_G	boolean := true
WRITE_EN_G	boolean := true
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 32 := 8
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
RX_CRC_PIPELINE_G	natural range 0 to 1 := 0
AXIL_CLK_FREQ_G	real := 125 . 0E + 6

Ports
pgpTxClk	in	sl
pgpTxRst	in	sl
pgpTxIn	in	Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOut	out	Pgp4TxOutType
pgpTxMasters	in	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
phyTxActive	in	sl
phyTxReady	in	sl
phyTxValid	out	sl := ' 0 '
phyTxStart	out	sl := ' 0 '
phyTxData	out	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyTxHeader	out	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
phyTxFecByp	out	sl := ' 1 '
pgpRxClk	in	sl
pgpRxRst	in	sl
pgpRxIn	in	Pgp4RxInType := PGP4_RX_IN_INIT_C
pgpRxOut	out	Pgp4RxOutType
pgpRxMasters	out	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpRxCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
phyRxClk	in	sl
phyRxRst	in	sl
phyRxInit	out	sl := ' 0 '
phyRxActive	in	sl
phyRxValid	in	sl
phyRxHeader	in	slv ( 1 downto 0 )
phyRxData	in	slv ( 63 downto 0 )
phyRxStartSeq	in	sl
phyRxSlip	out	sl := ' 0 '
phyRxFecByp	out	sl := ' 1 '
phyRxFecInjErr	out	sl := ' 0 '
phyRxFecLock	in	sl := ' 0 '
phyRxFecCorInc	in	sl := ' 0 '
phyRxFecUnCorInc	in	sl := ' 0 '
loopback	out	slv ( 2 downto 0 )
txDiffCtrl	out	slv ( 4 downto 0 )
txPreCursor	out	slv ( 4 downto 0 )
txPostCursor	out	slv ( 4 downto 0 )
txPolarity	out	sl
rxPolarity	out	sl
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4Core.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4Core.vhd