Pgp2fcTx.Pgp2fcTx Architecture Reference

Architecture >> Pgp2fcTx::Pgp2fcTx

Processes
PROCESS_323	( pgpTxClk )

Signals
cellTxSOC	sl
cellTxSOF	sl
cellTxEOC	sl
cellTxEOF	sl
cellTxEOFE	sl
cellTxData	slv ( 15 downto 0 )
schTxSOF	sl
schTxEOF	sl
schTxIdle	sl
schTxReq	sl
schTxAck	sl
schTxDataVc	slv ( 1 downto 0 )
intTxLinkReady	sl
intTxBusy	sl
schTxTimeout	sl
intPhyTxData	slv ( 15 downto 0 )
intPhyTxDataK	slv ( 1 downto 0 )
crcTxIn	slv ( 15 downto 0 )
crcTxInit	sl
crcTxValid	sl
crcTxOut	slv ( 31 downto 0 )
crcTxOutAdjust	slv ( 31 downto 0 )
crcTxRst	sl
crcTxInAdjust	slv ( 31 downto 0 )
crcTxWidthAdjust	slv ( 2 downto 0 )
intTxSof	slv ( 3 downto 0 )
intTxEofe	slv ( 3 downto 0 )
intvalid	slv ( 3 downto 0 )
rawReady	slv ( 3 downto 0 )
syncLocPause	slv ( 3 downto 0 )
syncLocOverFlow	slv ( 3 downto 0 )
syncRemPause	slv ( 3 downto 0 )
gateRemPause	slv ( 3 downto 0 )
syncLocLinkReady	sl
intTxMasters	AxiStreamMasterArray ( 3 downto 0 )
intTxSlaves	AxiStreamSlaveArray ( 3 downto 0 )
intFcSent	sl

Attributes
KEEP_HIERARCHY	string
KEEP_HIERARCHY	U_Pgp2fcTxSchedU_Pgp2fcTxCellTx_CRC : label is " TRUE "

Instantiations
u_sync	SynchronizerVector <Entity SynchronizerVector>
u_linkready	Synchronizer <Entity Synchronizer>
u_pgp2fctxphy	Pgp2fcTxPhy <Entity Pgp2fcTxPhy>
u_pgp2fctxsched	Pgp2fcTxSched <Entity Pgp2fcTxSched>
u_pgp2fctxcell	Pgp2fcTxCell <Entity Pgp2fcTxCell>
u_inputpipe	AxiStreamPipeline <Entity AxiStreamPipeline>
tx_crc	CRC32Rtl <Entity CRC32Rtl>

---

The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd