CRC32Rtl Entity Reference

Inheritance diagram for CRC32Rtl:

Entities
CRC32Rtl.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
CRC_INIT	slv ( 31 downto 0 ) := x " FFFFFFFF "

Ports
CRCOUT	out	slv ( 31 downto 0 )
CRCCLK	in	sl
CRCCLKEN	in	sl := ' 1 '
CRCDATAVALID	in	sl
CRCDATAWIDTH	in	slv ( 2 downto 0 )
CRCIN	in	slv ( 31 downto 0 )
CRCINIT	in	slv ( 31 downto 0 ) := CRC_INIT
CRCRESET	in	sl

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The documentation for this design unit was generated from the following files:

• base/crc/rtl/CRC32Rtl.vhd
• build/SRC_VHDL/surf/CRC32Rtl.vhd