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Pgp2fcGtp7Wrapper.rtl Architecture Reference
Architecture >> Pgp2fcGtp7Wrapper::rtl

Constants

PLL0_CFG_C  Gtp7QPllCfgType := ite ( TX_PLL_G = " PLL0 " , TX_PLL_CFG_G , RX_PLL_CFG_G )
PLL1_CFG_C  Gtp7QPllCfgType := ite ( TX_PLL_G = " PLL1 " , TX_PLL_CFG_G , RX_PLL_CFG_G )
SIM_GTRESET_SPEEDUP_C  string := ite ( SIM_GTRESET_SPEEDUP_G , " TRUE " , " FALSE " )

Signals

gtClk0  sl := ' 0 '
gtClk0Div2  sl
gtClk1  sl := ' 0 '
gtClk1Div2  sl
txRefClk  sl := ' 0 '
txOutClk  sl := ' 0 '
rxRefClk  sl := ' 0 '
stableClkRef  sl := ' 0 '
stableClkRefG  sl := ' 0 '
stableClk  sl := ' 0 '
stableRst  sl := ' 0 '
pgpTxClkBase  sl
pgpTxClk  sl
pgpTxReset  sl
pgpTxMmcmReset  sl
pgpTxMmcmLocked  sl
pgpRxRecClk  sl
pgpRxRecClkRst  sl
pgpRxClkLoc  sl
pgpRxReset  sl
pgpRxMmcmReset  sl
pgpRxMmcmLocked  sl
qPllRefClk  slv ( 1 downto 0 ) := " 00 "
qPllOutClk  slv ( 1 downto 0 ) := " 00 "
qPllOutRefClk  slv ( 1 downto 0 ) := " 00 "
qPllLock  slv ( 1 downto 0 ) := " 00 "
qPllLockDetClk  slv ( 1 downto 0 ) := " 00 "
qPllRefClkLost  slv ( 1 downto 0 ) := " 00 "
qPllReset  slv ( 1 downto 0 ) := " 00 "
locAxilWriteMasters  AxiLiteWriteMasterArray ( 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
locAxilWriteSlaves  AxiLiteWriteSlaveArray ( 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_INIT_C )
locAxilReadMasters  AxiLiteReadMasterArray ( 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
locAxilReadSlaves  AxiLiteReadSlaveArray ( 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_INIT_C )

Instantiations

ibufds_gte2_0  ibufds_gte2
ibufds_gte2_1  ibufds_gte2
bufg_stableclkref  bufg
pwruprst_inst  PwrUpRst <Entity PwrUpRst>
clockmanager7_tx  ClockManager7 <Entity ClockManager7>
bufg_pgptxclk  bufg
rstsync_pgptxrst  RstSync <Entity RstSync>
rstsync_pgprxrst  RstSync <Entity RstSync>
u_gtp7quadpll_1  Gtp7QuadPll <Entity Gtp7QuadPll>
pgp2fcgtp7_inst  Pgp2fcGtp7 <Entity Pgp2fcGtp7>
clockmanager7_1  ClockManager7 <Entity ClockManager7>
rstsync_1  RstSync <Entity RstSync>
u_axilitecrossbar_1  AxiLiteCrossbar <Entity AxiLiteCrossbar>

The documentation for this design unit was generated from the following file: