Gtp7QuadPll Entity Reference

Inheritance diagram for Gtp7QuadPll:

Collaboration diagram for Gtp7QuadPll:

Entities
Gtp7QuadPll.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_RESET_SPEEDUP_G	string := " TRUE "
SIM_VERSION_G	string := " 1.0 "
PLL0_REFCLK_SEL_G	bit_vector := " 001 "
PLL0_FBDIV_IN_G	integer range 1 to 5 := 4
PLL0_FBDIV_45_IN_G	integer range 4 to 5 := 5
PLL0_REFCLK_DIV_IN_G	integer range 1 to 2 := 1
PLL1_REFCLK_SEL_G	bit_vector := " 001 "
PLL1_FBDIV_IN_G	integer range 1 to 5 := 4
PLL1_FBDIV_45_IN_G	integer range 4 to 5 := 5
PLL1_REFCLK_DIV_IN_G	integer range 1 to 2 := 1
EN_DRP_G	boolean := true

Ports
qPllRefClk	in	slv ( 1 downto 0 )
qPllOutClk	out	slv ( 1 downto 0 )
qPllOutRefClk	out	slv ( 1 downto 0 )
qPllLock	out	slv ( 1 downto 0 )
qPllLockDetClk	in	slv ( 1 downto 0 )
qPllRefClkLost	out	slv ( 1 downto 0 )
qPllPowerDown	in	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
qPllReset	in	slv ( 1 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtp7/rtl/Gtp7QuadPll.vhd