Gtp7QuadPll.mapping Architecture Reference

Architecture >> Gtp7QuadPll::mapping

Signals
gtRefClk0	sl
gtRefClk1	sl
gtEastRefClk0	sl
gtEastRefClk1	sl
gtWestRefClk0	sl
gtWestRefClk1	sl
gtGRefClk0	sl
gtGRefClk1	sl
drpEn	sl := ' 0 '
drpWe	sl := ' 0 '
drpRdy	sl := ' 0 '
drpAddr	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
drpDi	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )

Instantiations
gtpe2_common_0_i	gtpe2_common
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtp7/rtl/Gtp7QuadPll.vhd