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Pgp2fcGthCoreWrapper.mapping Architecture Reference
Architecture >> Pgp2fcGthCoreWrapper::mapping

Components

Pgp2fcGthCore 

Constants

AXI_CROSSBAR_MASTERS_CONFIG_C  AxiLiteCrossbarMasterConfigArray ( 1 downto 0 ) := ( 0 = > ( baseAddr = > ( AXI_BASE_ADDR_G ) , addrBits = > 12 , connectivity = > x " FFFF " ) , 1 = > ( baseAddr = > ( AXI_BASE_ADDR_G+ x " 1000 " ) , addrBits = > 12 , connectivity = > x " FFFF " ) )

Signals

axilWriteMasters  AxiLiteWriteMasterArray ( 1 downto 0 )
axilWriteSlaves  AxiLiteWriteSlaveArray ( 1 downto 0 )
axilReadMasters  AxiLiteReadMasterArray ( 1 downto 0 )
axilReadSlaves  AxiLiteReadSlaveArray ( 1 downto 0 )
mAxilWriteMaster  AxiLiteWriteMasterType
mAxilWriteSlave  AxiLiteWriteSlaveType
mAxilReadMaster  AxiLiteReadMasterType
mAxilReadSlave  AxiLiteReadSlaveType
drpAddr  slv ( 9 downto 0 ) := ( others = > ' 0 ' )
drpDi  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpEn  sl := ' 0 '
drpWe  sl := ' 0 '
drpRdy  sl := ' 0 '
dummy0_6  slv ( 5 downto 0 ) := ( others = > ' 0 ' )
dummy1_14  slv ( 13 downto 0 ) := ( others = > ' 0 ' )
dummy2_14  slv ( 13 downto 0 ) := ( others = > ' 0 ' )
dummy3_6  slv ( 5 downto 0 ) := ( others = > ' 0 ' )
dummy4_1  sl := ' 0 '
dummy5_1  sl := ' 0 '
txctrl2  slv ( 7 downto 0 ) := ( others = > ' 0 ' )
cPllRefClkSel  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
cPllFbClkLost  sl := ' 0 '
cPllLock  sl := ' 0 '
cPllRefClkLost  sl := ' 0 '
rxCdrReset  sl := ' 0 '
rxPcsReset  sl := ' 0 '
rxPmaReset  sl := ' 0 '
txPcsReset  sl := ' 0 '
txPmaReset  sl := ' 0 '
rxPmaResetDoneInt  sl := ' 0 '
rxResetDoneInt  sl := ' 0 '
txPmaResetDone  sl := ' 0 '
rxByteIsAligned  sl := ' 0 '
rxByteReAlign  sl := ' 0 '
rxCommaDet  sl := ' 0 '
txUsrActive  sl := ' 0 '
rxUsrActive  sl := ' 0 '
rxMcommaAlignEn  sl := ' 1 '
rxPcommaAlignEn  sl := ' 1 '
buffBypassTxReset  sl := ' 0 '
buffBypassTxStart  sl := ' 0 '
buffBypassTxDone  sl := ' 0 '
buffBypassTxError  sl := ' 0 '
buffBypassRxReset  sl := ' 0 '
buffBypassRxStart  sl := ' 0 '
buffBypassRxDone  sl := ' 0 '
buffBypassRxError  sl := ' 0 '
rxDlysResetDone  sl := ' 0 '
rxPhyAlignDone  sl := ' 0 '
rxSyncDone  sl := ' 0 '
txResetGt  sl := ' 0 '
rxResetGt  sl := ' 0 '
rxResetAlignCheck  sl := ' 0 '
rstSyncRxIn  sl := ' 0 '
rxStatusLocked  sl := ' 0 '
rxOutClkGt  sl := ' 0 '
txOutClkGt  sl := ' 0 '
rxOutClkB  sl := ' 0 '
txOutClkB  sl := ' 0 '

Instantiations

u_pgp2fcgthcore  pgp2fcgthcore
rxoutclk_bufg_gt  bufg_gt
u_xbar  AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_aligncheck  GtRxAlignCheck <Entity GtRxAlignCheck>
u_axilitetodrp_1  AxiLiteToDrp <Entity AxiLiteToDrp>
u_rstsynctx  RstSync <Entity RstSync>
u_rstsyncrx  RstSync <Entity RstSync>

The documentation for this design unit was generated from the following file: