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Pgp2bGth7MultiLane.rtl Architecture Reference
Architecture >> Pgp2bGth7MultiLane::rtl

Signals

gtQPllResets  slv ( ( LANE_CNT_G- 1 ) downto 0 )
cPllLock  slv ( ( LANE_CNT_G- 1 ) downto 0 )
pgpRxMmcmResets  slv ( ( LANE_CNT_G- 1 ) downto 0 )
pgpRxRecClock  slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtRxResetDone  slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtRxUserReset  sl
gtRxUserResetIn  sl
phyRxLanesIn  Pgp2bRxPhyLaneInArray ( ( LANE_CNT_G- 1 ) downto 0 )
phyRxLanesOut  Pgp2bRxPhyLaneOutArray ( ( LANE_CNT_G- 1 ) downto 0 )
phyRxReady  sl
phyRxInit  sl
rxChBondLevel  slv ( 2 downto 0 )
rxChBondIn  Slv5Array ( LANE_CNT_G- 1 downto 0 )
rxChBondOut  Slv5Array ( LANE_CNT_G- 1 downto 0 )
pgpTxMmcmResets  slv ( ( LANE_CNT_G- 1 ) downto 0 )
pgpTxRecClock  slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtTxResetDone  slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtTxUserResetIn  sl
phyTxLanesOut  Pgp2bTxPhyLaneOutArray ( ( LANE_CNT_G- 1 ) downto 0 )
phyTxReady  sl
stableRst  sl
drpGnt  slv ( LANE_CNT_G- 1 downto 0 )
drpRdy  slv ( LANE_CNT_G- 1 downto 0 )
drpEn  slv ( LANE_CNT_G- 1 downto 0 )
drpWe  slv ( LANE_CNT_G- 1 downto 0 )
drpAddr  Slv9Array ( LANE_CNT_G- 1 downto 0 )
drpDi  Slv16Array ( LANE_CNT_G- 1 downto 0 )
drpDo  Slv16Array ( LANE_CNT_G- 1 downto 0 )

Instantiations

u_pgp2blane  Pgp2bLane <Entity Pgp2bLane>
gth7core_inst  Gth7Core <Entity Gth7Core>
u_axilitetodrp  AxiLiteToDrp <Entity AxiLiteToDrp>
u_rstsync  RstSync <Entity RstSync>

The documentation for this design unit was generated from the following file: