Architecture >> Gtp7Core::rtl
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RX_SYSCLK_SEL_C   | slv :=    ite (    RX_PLL_G =    " PLL0 " ,    " 00 " ,    " 11 " )  | 
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TX_SYSCLK_SEL_C   | slv :=    ite (    TX_PLL_G =    " PLL0 " ,    " 00 " ,    " 11 " )  | 
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RX_PLL0_USED_C   | boolean := (    RX_PLL_G =    " PLL0 " )  | 
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TX_PLL0_USED_C   | boolean := (    TX_PLL_G =    " PLL0 " )  | 
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RX_XCLK_SEL_C   | string :=    ite (    RX_BUF_EN_G ,    " RXREC " ,    " RXUSR " )  | 
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TX_XCLK_SEL_C   | string :=    ite (    TX_BUF_EN_G ,    " TXOUT " ,    " TXUSR " )  | 
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RX_OUTCLK_SEL_C   | bit_vector :=    getOutClkSelVal (  RX_OUTCLK_SRC_G )  | 
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TX_OUTCLK_SEL_C   | bit_vector :=    getOutClkSelVal (  TX_OUTCLK_SRC_G )  | 
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RX_DATA_WIDTH_C   | integer :=    getDataWidth (    RX_8B10B_EN_G ,    RX_EXT_DATA_WIDTH_G )  | 
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TX_DATA_WIDTH_C   | integer :=    getDataWidth (    TX_8B10B_EN_G ,    TX_EXT_DATA_WIDTH_G )  | 
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GT_TYPE_C   | string :=    " GTP "  | 
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WAIT_TIME_CDRLOCK_C   | integer :=    ite (    SIM_GTRESET_SPEEDUP_G =    " TRUE " ,   16  ,   165520  )  | 
The documentation for this design unit was generated from the following file:
- xilinx/7Series/gtp7/rtl/Gtp7Core.vhd