Gtp7RxRst Entity Reference

Inheritance diagram for Gtp7RxRst:

Collaboration diagram for Gtp7RxRst:

Entities
Gtp7RxRst.RTL	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
TPD_G	time := 1 ns
DYNAMIC_QPLL_G	boolean := false
SIMULATION_G	boolean := false
STABLE_CLOCK_PERIOD	integer range 4 to 20 := 8
RETRY_COUNTER_BITWIDTH	integer range 2 to 8 := 8
TX_PLL0_USED	boolean := false
RX_PLL0_USED	boolean := false

Ports
qPllRxSelect	in	std_logic_vector ( 1 downto 0 )
qPllTxSelect	in	std_logic_vector ( 1 downto 0 )
STABLE_CLOCK	in	std_logic
RXUSERCLK	in	std_logic
SOFT_RESET	in	std_logic
RXPMARESETDONE	in	std_logic
RXOUTCLK	in	std_logic
PLL0REFCLKLOST	in	std_logic
PLL1REFCLKLOST	in	std_logic
PLL0LOCK	in	std_logic
PLL1LOCK	in	std_logic
RXRESETDONE	in	std_logic
MMCM_LOCK	in	std_logic
RECCLK_STABLE	in	std_logic
RECCLK_MONITOR_RESTART	in	std_logic := ' 0 '
DATA_VALID	in	std_logic
TXUSERRDY	in	std_logic
DONT_RESET_ON_DATA_ERROR	in	std_logic := ' 0 '
GTRXRESET	out	std_logic := ' 0 '
MMCM_RESET	out	std_logic := ' 1 '
PLL0_RESET	out	std_logic := ' 0 '
PLL1_RESET	out	std_logic := ' 0 '
RX_FSM_RESET_DONE	out	std_logic
RXUSERRDY	out	std_logic := ' 0 '
RUN_PHALIGNMENT	out	std_logic
PHALIGNMENT_DONE	in	std_logic
RESET_PHALIGNMENT	out	std_logic := ' 0 '
RXDFEAGCHOLD	out	std_logic := ' 0 '
RXDFELFHOLD	out	std_logic := ' 0 '
RXLPMLFHOLD	out	std_logic := ' 0 '
RXLPMHFHOLD	out	std_logic := ' 0 '
RETRY_COUNTER	out	std_logic_vector ( RETRY_COUNTER_BITWIDTH- 1 downto 0 ) := ( others = > ' 0 ' )

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd