Architecture >> CoaXPressCoreWrapper::rtl

Constants
DATA_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 4 )
CFG_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 32 )

Signals
cfgIbMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
cfgIbSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
cfgObMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
cfgObSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
dataMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
dataSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
hdrMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
hdrSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
rxClkVec	slv ( 0 downto 0 )
rxRstVec	slv ( 0 downto 0 )
rxDataVec	slv32Array ( 0 downto 0 )
rxDataKVec	Slv4Array ( 0 downto 0 )
rxDispErrVec	slv ( 0 downto 0 )
rxDecErrVec	slv ( 0 downto 0 )
rxLinkUpVec	slv ( 0 downto 0 )
unusedClk	sl
unusedRst	sl

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_cfgib	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_cfgob	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_data	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_hdr	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	CoaXPressCore <Entity CoaXPressCore>

The documentation for this design unit was generated from the following file:

Constants

Signals