CoaXPressCore Entity Reference

Inheritance diagram for CoaXPressCore:

Collaboration diagram for CoaXPressCore:

Entities
CoaXPressCore.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
CoaXPressPkg	Package <CoaXPressPkg>

Generics
TPD_G	time := 1 ns
NUM_LANES_G	positive range 1 to 8 := 1
STATUS_CNT_WIDTH_G	positive range 1 to 32 := 12
RX_FSM_CNT_WIDTH_G	positive range 1 to 24 := 16
AXIL_CLK_FREQ_G	real := 156 . 25E + 6
AXIS_CLK_FREQ_G	real := 156 . 25E + 6
DATA_AXIS_CONFIG_G	AxiStreamConfigType
CFG_AXIS_CONFIG_G	AxiStreamConfigType

Ports
gtRstAll	out	sl
dataClk	in	sl
dataRst	in	sl
dataMaster	out	AxiStreamMasterType
dataSlave	in	AxiStreamSlaveType
imageHdrMaster	out	AxiStreamMasterType
imageHdrSlave	in	AxiStreamSlaveType
cfgClk	in	sl
cfgRst	in	sl
cfgIbMaster	in	AxiStreamMasterType
cfgIbSlave	out	AxiStreamSlaveType
cfgObMaster	out	AxiStreamMasterType
cfgObSlave	in	AxiStreamSlaveType
txClk	in	sl
txRst	in	sl
txLsValid	out	sl
txLsData	out	slv ( 7 downto 0 )
txLsDataK	out	sl
txLsRate	out	sl
txLsLaneEn	out	slv ( 3 downto 0 )
txTrig	in	sl
txLinkUp	in	sl
rxClk	in	slv ( NUM_LANES_G- 1 downto 0 )
rxRst	in	slv ( NUM_LANES_G- 1 downto 0 )
rxData	in	slv32Array ( NUM_LANES_G- 1 downto 0 )
rxDataK	in	Slv4Array ( NUM_LANES_G- 1 downto 0 )
rxDispErr	in	slv ( NUM_LANES_G- 1 downto 0 )
rxDecErr	in	slv ( NUM_LANES_G- 1 downto 0 )
rxLinkUp	in	slv ( NUM_LANES_G- 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/core/rtl/CoaXPressCore.vhd