ClinkData.rtl Architecture Reference

Architecture >> ClinkData::rtl

Processes
comb	( clinkRst , parClock , r , rstFsm )
seq	( clinkClk )

Constants
REG_INIT_C	RegType := ( state = > RESET_S , lastClk = > ( others = > ' 0 ' ) , delay = > toSlv ( 10 , 5 ) , delayLd = > ' 0 ' , bitSlip = > ' 0 ' , count = > 99 , status = > CL_LINK_STATUS_INIT_C )

Types
LinkState	( RESET_S , WAIT_C_S , SHIFT_C_S , CHECK_C_S , LOAD_C_S , SHIFT_D_S , CHECK_D_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rstFsm	sl
clinkClk	sl
clinkRst	sl
intData	slv ( 27 downto 0 )
parClock	slv ( 6 downto 0 )

Records
RegType

Instantiations
u_datashift	ClinkDataShift <Entity ClinkDataShift>
u_rstsync	RstSync <Entity RstSync>
u_datafifo	Fifo <Entity Fifo>
u_locked	Synchronizer <Entity Synchronizer>
u_delay	SynchronizerVector <Entity SynchronizerVector>
u_shiftcnt	SynchronizerVector <Entity SynchronizerVector>

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The documentation for this design unit was generated from the following file:

• protocols/clink/rtl/ClinkData.vhd