AxiStreamTapIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamTapIpIntegrator::rtl

Signals
axisAResetN	sl := ' 1 '
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
tsAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
tsAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
tmAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
tmAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_tapinsertslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_tapmaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_mainmaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiStreamTap <Entity AxiStreamTap>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd