AxiStreamTap Entity Reference

Inheritance diagram for AxiStreamTap:

Collaboration diagram for AxiStreamTap:

Entities
AxiStreamTap.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
ArbiterPkg	Package <ArbiterPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
TAP_DEST_G	natural range 0 to 255 := 0
PIPE_STAGES_G	natural range 0 to 16 := 0
ILEAVE_ON_NOTVALID_G	boolean := false
ILEAVE_REARB_G	natural := 0

Ports
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
tmAxisMaster	out	AxiStreamMasterType
tmAxisSlave	in	AxiStreamSlaveType
tsAxisMaster	in	AxiStreamMasterType
tsAxisSlave	out	AxiStreamSlaveType
axisClk	in	sl
axisRst	in	sl

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamTap.vhd
• build/SRC_VHDL/surf/AxiStreamTap.vhd