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AxiStreamTapIpIntegrator Entity Reference
+ Inheritance diagram for AxiStreamTapIpIntegrator:
+ Collaboration diagram for AxiStreamTapIpIntegrator:

Entities

AxiStreamTapIpIntegrator.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>

Generics

TPD_G  time := 1 ns
RST_POLARITY_G  sl := ' 1 '
RST_ASYNC_G  boolean := false
TAP_DEST_G  natural range 0 to 255 := 5
PIPE_STAGES_G  natural range 0 to 16 := 0
ILEAVE_ON_NOTVALID_G  boolean := false
ILEAVE_REARB_G  natural := 0
DATA_BYTES_G  positive := 4

Ports

axisClk   in   sl
axisRst   in   sl
S_AXIS_TVALID   in   sl := ' 0 '
S_AXIS_TDATA   in   slv ( DATA_BYTES_G* 8 - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP   in   slv ( DATA_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST   in   sl := ' 0 '
S_AXIS_TDEST   in   slv ( 7 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID   in   slv ( 7 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER   in   slv ( 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY   out   sl
TS_AXIS_TVALID   in   sl := ' 0 '
TS_AXIS_TDATA   in   slv ( DATA_BYTES_G* 8 - 1 downto 0 ) := ( others = > ' 0 ' )
TS_AXIS_TKEEP   in   slv ( DATA_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
TS_AXIS_TLAST   in   sl := ' 0 '
TS_AXIS_TDEST   in   slv ( 7 downto 0 ) := ( others = > ' 0 ' )
TS_AXIS_TID   in   slv ( 7 downto 0 ) := ( others = > ' 0 ' )
TS_AXIS_TUSER   in   slv ( 1 downto 0 ) := ( others = > ' 0 ' )
TS_AXIS_TREADY   out   sl
TM_AXIS_TVALID   out   sl
TM_AXIS_TDATA   out   slv ( DATA_BYTES_G* 8 - 1 downto 0 )
TM_AXIS_TKEEP   out   slv ( DATA_BYTES_G- 1 downto 0 )
TM_AXIS_TLAST   out   sl
TM_AXIS_TDEST   out   slv ( 7 downto 0 )
TM_AXIS_TID   out   slv ( 7 downto 0 )
TM_AXIS_TUSER   out   slv ( 1 downto 0 )
TM_AXIS_TREADY   in   sl := ' 0 '
M_AXIS_TVALID   out   sl
M_AXIS_TDATA   out   slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M_AXIS_TKEEP   out   slv ( DATA_BYTES_G- 1 downto 0 )
M_AXIS_TLAST   out   sl
M_AXIS_TDEST   out   slv ( 7 downto 0 )
M_AXIS_TID   out   slv ( 7 downto 0 )
M_AXIS_TUSER   out   slv ( 1 downto 0 )
M_AXIS_TREADY   in   sl := ' 0 '

The documentation for this design unit was generated from the following file: