AxiStreamRingBufferIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamRingBufferIpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 2 , tDestBits = > 1 , tUserBits = > 2 , tIdBits = > 1 )

Signals
axilResetN	sl := ' 1 '
axisResetN	sl := ' 1 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_m_axis	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_dut	AxiStreamRingBuffer <Entity AxiStreamRingBuffer>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd