AxiStreamRingBufferIpIntegrator Entity Reference

Inheritance diagram for AxiStreamRingBufferIpIntegrator:

Collaboration diagram for AxiStreamRingBufferIpIntegrator:

Entities
AxiStreamRingBufferIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns

Ports
dataClk	in	sl
dataRst	in	sl
dataValid	in	sl
dataValue	in	slv ( 15 downto 0 )
extTrig	in	sl
axilClk	in	sl
axilRst	in	sl
axisClk	in	sl
axisRst	in	sl
S_AXI_AWADDR	in	slv ( 7 downto 0 )
S_AXI_AWPROT	in	slv ( 2 downto 0 )
S_AXI_AWVALID	in	sl
S_AXI_AWREADY	out	sl
S_AXI_WDATA	in	slv ( 31 downto 0 )
S_AXI_WSTRB	in	slv ( 3 downto 0 )
S_AXI_WVALID	in	sl
S_AXI_WREADY	out	sl
S_AXI_BRESP	out	slv ( 1 downto 0 )
S_AXI_BVALID	out	sl
S_AXI_BREADY	in	sl
S_AXI_ARADDR	in	slv ( 7 downto 0 )
S_AXI_ARPROT	in	slv ( 2 downto 0 )
S_AXI_ARVALID	in	sl
S_AXI_ARREADY	out	sl
S_AXI_RDATA	out	slv ( 31 downto 0 )
S_AXI_RRESP	out	slv ( 1 downto 0 )
S_AXI_RVALID	out	sl
S_AXI_RREADY	in	sl
M_AXIS_TVALID	out	sl
M_AXIS_TDATA	out	slv ( 15 downto 0 )
M_AXIS_TKEEP	out	slv ( 1 downto 0 )
M_AXIS_TLAST	out	sl
M_AXIS_TDEST	out	slv ( 0 downto 0 )
M_AXIS_TID	out	slv ( 0 downto 0 )
M_AXIS_TUSER	out	slv ( 1 downto 0 )
M_AXIS_TREADY	in	sl

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd