AxiStreamFrameBuffer.rtl Architecture Reference

Architecture >> AxiStreamFrameBuffer::rtl

Functions
integer	get_n_buffs

Processes
dataComb	( dataR , dataRst , axilRstSync , dataValid , dataValue , dataFrameTxLast , rdReqSync , dataRdTrig , rdMoveDoneSync )
dataSeq	( dataClk , dataRst )
axiComb	( axilR , axilReadMaster , axilRst , dataRstSync , axilWriteMaster , ramRdData , rdFinalAddrSync , rdSetupDoneSync , txSlave , axilRdTrig )
axiSeq	( axilClk , axilRst )

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > DATA_BYTES_G , tKeepMode = > TKEEP_FIXED_C , tUserMode = > TUSER_FIRST_LAST_C , tDestBits = > 0 , tUserBits = > 2 , tIdBits = > 0 )
N_BUFFS_C	integer := get_n_buffs
DATA_REG_INIT_C	DataRegType := ( ramWrEn = > ' 0 ' , ramWrEnMask = > " 001 " , ramRdEnMask = > " 100 " , ramRdEnMaskNext = > " 100 " , rdSetupDone = > ' 0 ' , ramWrAddr = > ( others = > ' 0 ' ) , ramWrAddrNext = > ( others = > ' 0 ' ) , rdFinalAddr = > ( others = > ' 0 ' ) , rdFinalAddrNext = > ( others = > ' 0 ' ) , ramWrData = > ( others = > ' 0 ' ) , dataFrameTxLast = > ' 0 ' , dataFrameRxDone = > ' 0 ' , dataTrigState = > IDLE_S )
AXIL_REG_INIT_C	AxilRegType := ( softTrig = > ' 0 ' , rdReq = > ' 0 ' , rdFinalAddr = > ( others = > ' 0 ' ) , ramRdAddr = > ( others = > ' 0 ' ) , rdMoveDone = > ' 0 ' , rdEn = > " 000 " , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , txMaster = > axiStreamMasterInit ( AXIS_CONFIG_C ) , axisState = > IDLE_S , axisStateIdx = > ( others = > ' 0 ' ) )

Types
RamRdArray	array ( natural range <> ) of slv ( 8 * DATA_BYTES_G- 1 downto 0 )
DataTrigStateType	( IDLE_S , WAIT_S )
AxisStateType	( IDLE_S , DONE_S , MOVE_S )

Signals
ramRdDataArr	RamRdArray ( 2 downto 0 )
ramRdData	slv ( 8 * DATA_BYTES_G- 1 downto 0 )
dataR	DataRegType := DATA_REG_INIT_C
dataRin	DataRegType
axilR	AxilRegType := AXIL_REG_INIT_C
axilRin	AxilRegType
axilRstSync	sl
dataRstSync	sl
rdFinalAddrSync	slv ( RAM_ADDR_WIDTH_G- 1 downto 0 )
rdSetupDoneSync	sl
rdMoveDoneSync	sl
dataToAxilSyncIn	slv ( RAM_ADDR_WIDTH_G downto 0 )
dataToAxilSyncOut	slv ( RAM_ADDR_WIDTH_G downto 0 )
axilToDataSyncIn	slv ( 1 downto 0 )
axilToDataSyncOut	slv ( 1 downto 0 )
rdReqSync	sl
txSlave	AxiStreamSlaveType
ramWrEnMasked	sl

Records
DataRegType
AxilRegType

Instantiations
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_rstsync_axilrst	RstSync <Entity RstSync>
u_rstsync_datarst	RstSync <Entity RstSync>
u_syncvec_datatoaxil	SynchronizerVector <Entity SynchronizerVector>
u_syncvec_axiltodata	SynchronizerVector <Entity SynchronizerVector>
tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/rtl/AxiStreamFrameBuffer.vhd