Architecture >> AxiStreamDma::structure

Processes
PROCESS_23	( axiClk )
PROCESS_24	( axiRst , ib , intReadMasters , intWriteMasters , ob , popFifoValid , r )
PROCESS_25	( axiRst , ib , ibAck , popFifoPFull , pushFifoDout , pushFifoValid , r )
PROCESS_26	( axiRst , ob , obAck , pushFifoDout , pushFifoValid , r )
PROCESS_81	( axiClk )
PROCESS_82	( axiRst , ib , intReadMasters , intWriteMasters , ob , popFifoValid , r )
PROCESS_83	( axiRst , ib , ibAck , popFifoPFull , pushFifoDout , pushFifoValid , r )
PROCESS_84	( axiRst , ob , obAck , pushFifoDout , pushFifoValid , r )

Constants
PUSH_ADDR_WIDTH_C	integer := FREE_ADDR_WIDTH_G
POP_ADDR_WIDTH_C	integer := FREE_ADDR_WIDTH_G
POP_FIFO_PFULL_C	integer := ( 2 POP_ADDR_WIDTH_C ) - 10**
POP_FIFO_COUNT_C	integer := 2
PUSH_FIFO_COUNT_C	integer := 2
IB_FIFO_C	integer := 0
OB_FIFO_C	integer := 1
CROSSBAR_CONN_C	slv ( 15 downto 0 ) := x " FFFF "
LOC_INDEX_C	natural := 0
LOC_BASE_ADDR_C	slv ( 31 downto 0 ) := AXIL_BASE_ADDR_G ( 31 downto 12 ) & x " 000 "
LOC_NUM_BITS_C	natural := 10
FIFO_INDEX_C	natural := 1
FIFO_BASE_ADDR_C	slv ( 31 downto 0 ) := AXIL_BASE_ADDR_G ( 31 downto 12 ) & x " 400 "
FIFO_NUM_BITS_C	natural := 10
AXI_CROSSBAR_MASTERS_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( 1 downto 0 ) := ( LOC_INDEX_C = > ( baseAddr = > LOC_BASE_ADDR_C , addrBits = > LOC_NUM_BITS_C , connectivity = > CROSSBAR_CONN_C ) , FIFO_INDEX_C = > ( baseAddr = > FIFO_BASE_ADDR_C , addrBits = > FIFO_NUM_BITS_C , connectivity = > CROSSBAR_CONN_C ) )
REG_INIT_C	RegType := ( maxRxSize = > ( others = > ' 0 ' ) , interrupt = > ' 0 ' , intEnable = > ' 0 ' , intAck = > ' 0 ' , acknowledge = > ' 0 ' , online = > ' 0 ' , rxEnable = > ' 0 ' , txEnable = > ' 0 ' , fifoClear = > ' 1 ' , swCache = > AXI_CACHE_G , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )
IB_INIT_C	IbType := ( state = > IDLE_S , intPending = > ' 0 ' , ibReq = > AXI_WRITE_DMA_REQ_INIT_C , popFifoWrite = > ' 0 ' , popFifoDin = > ( others = > ' 0 ' ) , pushFifoRead = > ' 0 ' )
OB_INIT_C	ObType := ( state = > IDLE_S , intPending = > ' 0 ' , obReq = > AXI_READ_DMA_REQ_INIT_C , popFifoWrite = > ' 0 ' , popFifoDin = > ( others = > ' 0 ' ) , pushFifoRead = > ' 0 ' )

Types
StateType	( IDLE_S , WAIT_S , FIFO_0_S , FIFO_1_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
ib	IbType := IB_INIT_C
ibin	IbType
ob	ObType := OB_INIT_C
obin	ObType
intReadMasters	AxiLiteReadMasterArray ( 1 downto 0 )
intReadSlaves	AxiLiteReadSlaveArray ( 1 downto 0 )
intWriteMasters	AxiLiteWriteMasterArray ( 1 downto 0 )
intWriteSlaves	AxiLiteWriteSlaveArray ( 1 downto 0 )
popFifoClk	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
popFifoRst	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
popFifoValid	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
popFifoWrite	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
popFifoPFull	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
popFifoDin	Slv32Array ( POP_FIFO_COUNT_C- 1 downto 0 )
pushFifoClk	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
pushFifoRst	slv ( POP_FIFO_COUNT_C- 1 downto 0 )
pushFifoValid	slv ( PUSH_FIFO_COUNT_C- 1 downto 0 )
pushFifoDout	Slv36Array ( PUSH_FIFO_COUNT_C- 1 downto 0 )
pushFifoRead	slv ( PUSH_FIFO_COUNT_C- 1 downto 0 )
obAck	AxiReadDmaAckType
obReq	AxiReadDmaReqType
ibAck	AxiWriteDmaAckType
ibReq	AxiWriteDmaReqType

Records
RegType
IbType
ObType

Instantiations
u_axicrossbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_swfifos	AxiLiteFifoPushPop <Entity AxiLiteFifoPushPop>
u_ibdma	AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_obdma	AxiStreamDmaRead <Entity AxiStreamDmaRead>
u_axicrossbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_swfifos	AxiLiteFifoPushPop <Entity AxiLiteFifoPushPop>
u_ibdma	AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_obdma	AxiStreamDmaRead <Entity AxiStreamDmaRead>

The documentation for this design unit was generated from the following files:

axi/dma/rtl/v1/AxiStreamDma.vhd
build/SRC_VHDL/surf/AxiStreamDma.vhd

Processes

Constants

Types

Signals

Records

Instantiations