AxiStreamDma Entity Reference

Inheritance diagram for AxiStreamDma:

Collaboration diagram for AxiStreamDma:

Entities
AxiStreamDma.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
FREE_ADDR_WIDTH_G	integer := 9
AXIL_COUNT_G	integer range 1 to 2 := 1
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := x " 00000000 "
AXI_READY_EN_G	boolean := false
AXIS_READY_EN_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
AXI_CONFIG_G	AxiConfigType
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 1111 "
PEND_THRESH_G	natural := 0
BYP_SHIFT_G	boolean := false

Ports
axiClk	in	sl
axiRst	in	sl
axilReadMaster	in	AxiLiteReadMasterArray ( AXIL_COUNT_G- 1 downto 0 )
axilReadSlave	out	AxiLiteReadSlaveArray ( AXIL_COUNT_G- 1 downto 0 )
axilWriteMaster	in	AxiLiteWriteMasterArray ( AXIL_COUNT_G- 1 downto 0 )
axilWriteSlave	out	AxiLiteWriteSlaveArray ( AXIL_COUNT_G- 1 downto 0 )
interrupt	out	sl
online	out	sl
acknowledge	out	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
mAxisCtrl	in	AxiStreamCtrlType
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
axiWriteCtrl	in	AxiCtrlType

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDma.vhd
• build/SRC_VHDL/surf/AxiStreamDma.vhd